Synchronous clock generator and time-base error corrector

Details Synchronous clock generator and time-base error corrector Synchronous clock generator and time-base error corrector

1992-11-25

1994-03-29

Groody, James J.

Television

Synchronization

Automatic phase or frequency control

358337, 331 20, 348148, 348525, H04N 504

Patent

active

052989984

ABSTRACT:
In a clock generator circuit, a zero hold circuit produces from a fixed clock signal a zero hold clock signal which is in phase with an external sync signal. A phase comparator circuit produces phase difference data indicating the phase difference between the external sync signal and an internal sync signal. A counter cleared by the external sync signal counts pulses of the zero hold clock signal to obtain count data. A memory receiving the phase difference data and the count data as its address input produces the internal sync signal when the count data is smaller than the number of pulses in one cycle of the external sync signal having no time-base variations, and a phase control signal determined by the phase difference data and the count data. A phase shifter shifts the phase of the zero hold clock according to the phase control signal to obtain a modified clock signal synchronized with the external sync signal.

REFERENCES:
patent: 4417218 (1983-11-01), Berke
patent: 4688094 (1987-08-01), Tanabe et al.
patent: 4989073 (1991-01-01), Wagner
patent: 5062005 (1991-10-01), Kitaura et al.
patent: 5168360 (1992-12-01), Maeshima
patent: 5184091 (1993-02-01), Srivastava

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