Synchronous clock generation circuit capable of ensuring...

Details Synchronous clock generation circuit capable of ensuring... Synchronous clock generation circuit capable of ensuring...

2006-06-20

2006-06-20

Chang, Joseph (Department: 2817)

Oscillators

Ring oscillators

C331S014000, C331S011000

Reexamination Certificate

active

07064621

ABSTRACT:
At a first step, in a synchronous clock generation circuit, the number of delay stages serving as a digital PLL circuit is increased/decreased, and an oscillation circuit performs an oscillation operation when an optimal number of delay stages is set. Thereafter, in an operation at a second step, a control voltage is controlled with the optimal number of delay stages being set for serving as an analog PLL circuit, thereby attaining a lock-in state. As the lock-in state is finally maintained under analog control, an excellent jitter characteristic can be obtained. Thus, ensuring a lock-in range that has been a problem in the analog PLL circuit is solved by varying the number of delay stages in the operation at the first step, and a high jitter characteristic that has been a problem in a digital PLL circuit can be solved by analog control in the operation at the second step.

REFERENCES:
patent: 6466100 (2002-10-01), Mullgrav et al.
patent: 6563387 (2003-05-01), Hirano et al.
patent: 05-110429 (1993-04-01), None
patent: 2001-144607 (2001-05-01), None
patent: 2002-152039 (2004-05-01), None

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