Synchronous clock distribution system

Details Synchronous clock distribution system Synchronous clock distribution system

1992-06-26

1996-01-02

Chin, Stephen

Pulse or digital communications

Synchronizers

Network synchronizing more than two stations

375376, 327149, 327150, 327153, 327159, 327163, 327231, 327291, 331 17, 331 25, 395550, H04L 700

Patent

active

054815738

ABSTRACT:
A clock signal distribution system for a digital electronic system operating at high clock speed and short cycle times distributes a primary clock signal which is of relatively low frequency through conventional hardware. A high frequency secondary clock signal is generated using a phase locked loop to maintain high accuracy synchronization with the primary clock. Delay means are provided for both the primary and secondary clock signals to provide compensation of propagation time or to provide desired offsets. The phase locked loop arrangements with delays can be cascaded to provide flexibility of both frequency and phase of signals throughout the system, any or all of which may be maintained in synchronism with the primary clock. A dynamic digital transfer function generator is also used within the phase locked loop to achieve particular synchronization functions. The signal distribution system can be used at any or all levels of a network or complex and partitioning of the network or complex may be done based on the articulation of the clock distribution system.

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