Synchronous circuit with clock skew compensating function and ci

Details Synchronous circuit with clock skew compensating function and ci Synchronous circuit with clock skew compensating function and ci

1992-07-13

1993-08-24

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 3072723, 307279, 307572, 307603, 377 79, H03K 3356, H03K 1722, H03K 513

Patent

active

052392066

ABSTRACT:
Disclosed here are D-type flipflops cascaded in a semicustom LSI such as a standard cell or a gate array. Clock signals supplied to each of the flipflops have phases different from each other due to clock skew. A signal indicative of a data signal holding in the flipflop in one stage is applied to the flipflop in the preceding stage. The flipflop in the preceding stage is responsive to the applied signal for allowing a data signal held in a master latch to be transmitted to a slave latch. As a result, the passing through of data which might be possibly caused by the clock skew can be prevented. In other words, the passing of a data signal through two flipflops during one clock cycle can be prevented.

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