Synchronous circuit of FM multiplex broadcasting receiver

Details Synchronous circuit of FM multiplex broadcasting receiver Synchronous circuit of FM multiplex broadcasting receiver

1999-02-22

2003-05-06

Kizou, Hassan (Department: 2662)

Multiplex communications

Communication over free space

Repeater

C370S350000, C370S503000, C342S357490, C455S208000

Reexamination Certificate

active

06560207

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronous circuit of an FM multiplex broadcasting receiver for receiving two or more FM signals, each of which includes FM multiplex data.
2. Description of the Related Art
Lately, car-navigation devices which enable a driver to know the present location of his vehicle on a map while driving by detecting the location using a relative or absolute measuring method have widely spread. In such car-navigation devices, two methods of measuring the location of a vehicle are adopted. One is a method of calculating a relative location from the starting point using a gyro sensor, an azimuth sensor, vehicle speed signals or the like, and this method is called self-contained navigation. The other is a method of calculating an absolute location using a global positioning system (GPS) satellite, and is called radio navigation.
Further, it has become possible to obtain road traffic information on the car navigation devices as well as to detect the present location of user's vehicle on the map as described above. More specifically, in Japan the Vehicle Information and Communication System (VICS) data service which is a road traffic information data service using FM multiplex broadcasting was inaugurated in 1996, whereby it is possible for the car-navigation devices to display information concerning traffic jams or other road data (suspension of traffic, road construction or the like) on the map based on the VICS data service.
In calculating an absolute location of a vehicle by a GPS satellite, there is a maximum error of 100 meters due to an intentional deterioration of accuracy which is produced to cope with a clock error of the satellite, an orbital error of the satellite, a delay error caused by an ionized layer, exploitation for criminal activities, or the like. In order to reduce such an error, a differential GPS (D-GPS) system has been developed. In this system, GPS radio waves are received by a reference broadcasting base station which has accurate data of the absolute location of a vehicle, an error between the absolute location and a location calculated based on the GPS radio waves is detected, information data of the error is transmitted to a car-navigation device using broadcasting radio waves, and then the car-navigation device obtains more accurate data concerning the location utilizing the error information data. The D-GPS (error information) data service by FM multiplex broadcasting as described above was inaugurated in 1997. With this service, it is possible to measure the location of a vehicle with a computational error of several meters.
Thus, when an FM multiplex broadcasting receiver of a car-navigation device receives VICS data or D-GPS data, a VICS data broadcasting station has to be switched to a D-GPS data broadcasting station, and vice versa.
FIG. 1
is a block diagram showing a standard FM multiplex broadcasting receiver. As the receiver shown in
FIG. 1
is well known, the description thereof will be omitted. Further,
FIG. 2
shows actual circuits of a block synchronous circuit and a frame synchronous circuit shown in FIG.
1
.
In
FIG. 2
, a data counter
101
is a 2.88 centesimal counter for block synchronization. It counts a system clock of 16 kHz (a clock having the same frequency as that of a bit rate of FM multiplex data) and outputs a pulse C
1
at every one block, namely, at an interval of 18 ms. Numeral
105
is a block identification code (BIC) detection circuit which detects a BIC from the data received. As will be described later, if a BIC is detected by the BIC detection circuit
105
while block synchronization is asynchronous, the data counter
101
will be reset.
Numeral
106
is a timing detection circuit which compares both the generation timing of an output pulse C
1
of the data counter
101
and an output pulse BP of the BIC detection circuit
105
and detects accord or disaccord of the generation timing. When both the generation timing of the pulse C
1
and the pulse BP accord, an accord pulse P
1
is outputted, whereas when both the generation timing disaccord, a disaccord pulse P
2
is outputted. Numeral
107
is a block synchronization determination protecting circuit. It outputs an output BL which is “1” representing that block synchronization has been established when the accord pulse P
1
is consecutively counted prescribed M times (the number of backward protection M), and outputs an output BL which is “zero” representing that block synchronization has stepped out when the disaccord pulse P
2
is consecutively counted prescribed N times (the number of forward protection N).
Numeral
109
is a BIC variable point detection circuit which detects a variable point of the BIC detected. For example, in FM multiplex data which constitute a frame as shown in
FIG. 3
, the BIC variable point detection circuit detects each variable point of BIC
1
to BIC
3
, BIC
4
to BIC
2
, BIC
2
to BIC
3
, and BIC
4
to BIC
1
. Numeral
110
is a 2.72 centesimal counter for frame synchronization and also a block counter which counts the number of blocks by counting output pulses C
1
of the data counter
101
. Numeral
111
is a frame synchronization detection protecting circuit. It compares a variable point detected by the BIC variable point detection circuit
109
with a variable point calculated based on a count value of the block counter
110
. When the variable points accord consecutively a prescribed number of times X (the number of backward protection X), it outputs an output FL which is “1” representing that frame synchronization has been established. When the variable points disaccord consecutively a prescribed number of times Y (the number of forward protection Y), it outputs an output FL which is “0” representing that frame synchronization has been lost. When frame synchronization is asynchronous, detection of a prescribed BIC variable point causes the block counter
110
to be set to a prescribed value. Further, an output FCK from the frame synchronization detection protecting circuit
111
is a frame top signal which is generated when the block counter finishes 2.72 centesimal counting under the condition of frame synchronization.
When the FM multiplex broadcasting receiver shown in
FIG. 1
attempts to obtain D-GPS data during the reception of data from a VICS data broadcasting station, the receiving frequency is temporarily switched from the VICS data broadcasting wave to a D-GPS data broadcasting wave and also block synchronization is carried out on the D-GPS data broadcasting wave, and then the receiving frequency is returned to the VICS data broadcasting wave again. Only the D-GPS data composed of two blocks are required for obtaining error information. Therefore, even though VICS data cannot be obtained during the reception of data from the D-GPS data broadcasting station, it is possible to restore the VICS data which could not be received during the reception of data from the D-GPS data broadcasting station by correcting errors in a vertical direction by vertical parity while composing a frame as shown in FIG.
3
.
However, in a conventional circuit shown in
FIG. 2
, when the receiving wave is returned from the D-GPS data broadcasting wave to the VICS data broadcasting wave, slippage of frame synchronization of the VICS data broadcasting wave arises, whereby frame synchronization of the VICS data broadcasting wave is lost. In this situation, it is impossible not only to restore, but also demodulate the VICS data which could not be received during the reception of data from the D-GPS data broadcasting station.
Next, loss of frame synchronization of the VICS data will further be described with reference to a timing chart shown in FIG.
4
. Incidentally, in this description it will be assumed that the number of backward protection M of a block synchronous circuit is two, the number of forward protection N of the block synchronous circuit is two, the number of backward protection X of a frame synchronous circuit is two, the number of forwar

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