Synchronous circuit and method for receiving data

Pulse or digital communications – Synchronizers – Synchronizing the sampling time of digital data

Reexamination Certificate

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Details

C375S371000, C375S354000, C375S322000, C375S360000, C375S366000, C370S480000, C370S506000, C370S522000

Reexamination Certificate

active

08054927

ABSTRACT:
The present invention includes: a synchronous-word detecting unit receives a baseband received signal including a synchronous word and data for each frame, and detects whether or not the synchronous word is coincided with an expected value in the baseband received signal by using an N-(N is an integer of 2 or larger) phase sampling clock; a phase information retaining unit retains phase information accumulatively including results detected for a plurality of frames by the synchronous-word detecting unit, and determines a phase to be sampled on the basis of the retained phase information; a phase selecting unit selects and determines a phase of the sampling clock on the basis of determination by the phase information retaining unit; and a FIFO buffer samples the data from the baseband received signal, and outputs the sampled data.

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patent: 6813325 (2004-11-01), Lin
patent: 7116735 (2006-10-01), Yamada et al.
patent: 7620072 (2009-11-01), Kihara
patent: 2002/0140867 (2002-10-01), Weiss
patent: 2003/0210756 (2003-11-01), Ito
patent: 2003-333020 (2003-11-01), None

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