Synchronous bus type semiconductor circuit wherein two control s

Details Synchronous bus type semiconductor circuit wherein two control s Synchronous bus type semiconductor circuit wherein two control s

1987-05-27

1988-07-26

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307262, 307470, 307265, 307601, 307606, 328 99, 328 55, H03K 1900, H03K 500, H03K 513, H03K 5159

Patent

active

047602910

ABSTRACT:
A semiconductor IC device of an asynchronous bus type which is in a selected state when a chip select signal applied to it is at a "H" level, comprises an external control signal line through which an external control signal is input, and a first and a second internal control signal lines for transfer of a first and a second control signals each of which is not activated when the other is activated. The first control signal is allocated to either the "H" level or the "L" level of the external control signal, and the second control signal is activated when the external control line is at the second level which is the inverse of the first level for the first control signal. An inhibit circuit is provided to prevent the second control signal from being erroneously activated while the first control signal is to be activated and when the first level of the external control signal begins after or terminates before the chip select signal.

REFERENCES:
patent: 3471790 (1969-10-01), Kaps
patent: 4317053 (1982-02-01), Shaw et al.
patent: 4691121 (1987-09-01), Theus
patent: 4719371 (1988-01-01), Fujita et al.
Intel, Component Data Catalog, 1982, 9-333.
Motorola Inc., 8-Bit Microprocessor & Peripheral Data; DL 133; 3-307, 309.

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