Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-05-28
2001-01-09
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S212000, C327S214000
Reexamination Certificate
active
06172539
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a synchronous buffer circuit and a data transmission circuit using the synchronous buffer circuit. More particularly, this invention is concerned with a synchronous bidirectional buffer circuit used to transfer data from or to a transmission line terminated by terminating resistors, and a data transmission circuit including the synchronous bidirectional buffer circuits.
In general, a low-amplitude level is often used as a fashion for transmitting data at a high speed over a transmission line. Since the adoption of a low amplitude enables minimization of reflection of a signal, fast transmission can be achieved. It is known that a conventional data transmission circuit is known as an exemplary data transmission circuit using a low-amplitude level.
Reflection of data occurs at terminals of a transmission line in the conventional data transmission circuit, as will be described later. It is therefore essential to absorb the reflection fully.
However, it is in practice very difficult to fully absorb reflection in the conventional data transmission circuit.
In order to reduce the reflection, a time instant at which an output level changes from a low level to a high level has been delayed on purpose in an effort to minimize reflection. An output waveform may be trimmed with respect to a slew rate in order to absorb a reflected wave. This method cannot help inviting a decrease in a data transmission rate.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a synchronous buffer circuit capable of transmitting data at a high speed with absorbing a reflected wave fully
It is another object of this invention to provide a data transmission circuit using the synchronous buffer circuit.
Other objects of this invention will become clear as the description proceeds.
According to a first aspect of this invention, there is provided a synchronous buffer circuit for outputting a buffered signal as an output signal to an output terminal in synchronous with a clock signal. The synchronous buffer circuit comprises a first latch circuit for latching the buffered signal as a first latched signal in response to first one of leading and trailing edges of the clock signal, a second latch circuit for latching the buffered signal as a second latched signal in response to second one of the leading and the trailing edges of the clock signal, and a producing circuit for producing the output signal in accordance with the first and the second latched signal.
According to a second aspect of this invention, there is provided a synchronous buffer circuit for outputting a buffered signal as an output signal to an output terminal in synchronous with a clock signal. The clock signal has first and second edges. The first edge is one of leading and trailing edge. The second edge is another one of the leading and the trailing edge. The synchronous buffer circuit comprises a latch circuit for latching the buffered signal as a latched signal in response to the first edge and producing means for producing a first one of high and low levels as the output signal until a next first edge is supplied, when the latched signal has a first logic level, the producing means producing a second one of the high and said low levels until the second edge is supplied, when the latched signal has a second logic level.
According to a third aspect of this invention, there is provided a data transmission circuit comprising a transmission path and a plurality of synchronous buffer circuits. A terminating voltage is applied to the transmission path through a terminating resistor. Each of the synchronous buffer circuits is electrically coupled to the transmission path. Each of the synchronous buffer circuits comprises first means for supplying the transmission path with a first voltage substantially equal to the terminating voltage, in synchronous with a clock signal, second means for supplying the transmission path with a second voltage substantially different from the terminating voltage, in synchronous with the clock signal, and third means for controlling the second means to make the second means supply the transmission path with the second voltage over a predetermined period during which the second voltage is synchronous with the clock signal, when an own synchronous buffer circuit transfers one of first and second logic levels to another synchronous buffer circuit in the predetermined period.
REFERENCES:
patent: 4775840 (1988-10-01), Ohmori et al.
patent: 4879693 (1989-11-01), Ferrant
patent: 5001374 (1991-03-01), Chang
patent: 5172397 (1992-12-01), Llewellyn
patent: 5179295 (1993-01-01), Mattison et al.
patent: 5729152 (1998-03-01), Leung et al.
patent: 5936429 (1999-08-01), Tomita
Dinh Paul
Hayes, Soloway,Hennessey, Grossman & Hage
NEC Corporation
Wells Kenneth B.
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