Synchronizing video formats with dissimilar timing

Details Synchronizing video formats with dissimilar timing Synchronizing video formats with dissimilar timing

2006-07-04

2006-07-04

Natnael, Paulos M. (Department: 3485)

Television

Synchronization

C327S147000

Reexamination Certificate

active

07071996

ABSTRACT:
In order to synchronize two dissimilar video formats, two or more phase locked loop circuits (PLL's) may be used in tandem. A first PLL circuit may be connected to the first video format (Master) and generate an intermediate frequency. A second PLL circuit may use the intermediate frequency as the timebase for generating the pixel clock for the second video format (Slave). One or more Slaves may be connected to the generated pixel clock. The video synchronizing device may be a part of a graphics system, such as a graphics accelerator.

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