Synchronizing unit for receiving section of PCM station

Multiplex communications – Wide area network – Packet switching

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H04J 308

Patent

active

043947581

ABSTRACT:
Incoming data words organized in a succession of multi-channel frames, arriving at a receiving section of a PCM station, are fed in parallel therewith to a correlation circuit forming part of a synchronizing unit which includes a timer stepped by line-clock pulses extracted from the incoming bit stream. The correlation circuit includes a decoder which recognizes predetermined bits or bit combinations in alignment words A and B respectively appearing at the beginning of alternate frames. Recurrent noncoincidences of either of these alignment words with a corresponding marking pulse emitted by the timer, in a time slot designating the No. 0 channel of a frame, causes a readjustment of the timer and thus a shifting of clock signals emitted thereby to the receiving section. The synchronizing unit, embodied in an integrated-circuit chip, further includes a malfunction detector responsive to signals emitted by the timer and by the decoder of the correlation circuit.

REFERENCES:
patent: 4002846 (1977-01-01), Barbier
patent: 4081611 (1978-03-01), Bovo et al.

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