Synchronizing two processors as an integral part of fault detect

Details Synchronizing two processors as an integral part of fault detect Synchronizing two processors as an integral part of fault detect

1991-08-26

1993-09-28

Beausoliel, Jr., Robert W.

Excavating

364132, 371 671, G06F 1540

Patent

active

052491889

ABSTRACT:
A central processing unit arrangement for detecting a fault in a central processing unit system that includes a master processor and a slave processor. Master and slave processors are resynchronized at every bus cycle by conditioning the processors' READY signal with the ADS (address status) signals from each processor (ADS indicates that an access cycle has begun and a valid address is present on the address bus). This method of synchronization was selected over the more traditional method of lock-step, which was deemed impractical to implement given the timing constraints of a high speed bus. Also, the dual processors may not always begin their respective bus cycles on the same clock. In addition, it is necessary to synchronize processors for the first instruction fetch following a reset, because the time of completion of an internal self-test may not be deterministic. After both ADS signals are received, the status of the master and slave buses are compared and a fault is detected if the buses are different. If a predetermined amount of time passes before both ADS signals are received then the processors are signaled to continue with the cycle. Because the processors are no longer synchronized, the buses will miscompare, thereby detecting a fault. Additional fault detection measures can be taken such as parity, checksum and EDAC.

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patent: 5161151 (1992-11-01), Kimura et al.

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