Pulse or digital communications – Synchronizers – Frequency or phase control using synchronizing signal
Reexamination Certificate
1998-11-24
2001-01-23
Chin, Stephen (Department: 2734)
Pulse or digital communications
Synchronizers
Frequency or phase control using synchronizing signal
C370S503000, C327S155000
Reexamination Certificate
active
06178214
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a synchronizing system which synchronizes a demodulated signal with a received signal and which is used in a radio base station of the TDMA-TDD type.
DESCRIPTION OF THE PRIOR ART
Generally, in the synchronizing system of the TDMA-TDD type, the synchronizing system of the radio base station receives, as a received signal, a transmitting signal (control channel signal) from the other radio base station to judge timing of the received signal and to synchronize a demodulated signal with the received signal. In the synchronizing system of the TDMA-TDD type, timing of transmitting signals are random and each of the received signals is a burst signal. The radio base station waits so as to receive, in series, the transmitting signals. The synchronizing system of the radio base station detects an edge of a RSSI (Received Signal Strength Intensity) level to produce an edge detecting signal when the RSSI level is greater than a predetermined threshold level. The synchronizing system of the radio base station starts, in response to the edge detecting signal, to operate as a bit synchronous circuit or an AFC circuit.
A conventional synchronizing system is disclosed in Japanese Unexamined Patent Prepublication (koukai) No.29910/1994. The conventional synchronizing system comprises a received frame separating circuit, a timing correcting circuit, and a transmitting frame generating circuit. The received frame separating circuit detects timing of a received signal to produce and supply a timing value signal to the timing correcting circuit. The timing correcting circuit corrects the timing value signal to produce and supply a corrected timing value signal to the transmitting frame generating circuit. The transmitting frame generating circuit generates, in response to the corrected timing value signal, a transmitting signal as a demodulated signal. Thereby, the conventional synchronizing system synchronizes the transmitting signal with the received signal.
In communication of the TDMA-TDD type, transmitting signals of each of the radio base stations are, apart, transmitted so that the transmitting signals are not overlapped. However, the radio base station is supplied with the radio signals which are overlapped or serial due to physical distance difference in air transfer or multiple fading. In this event, the RSSI level of the received signal which is received by the radio base station is not smaller than the predetermined level. As a result, the radio base station does not detect the edge of the RSSI level. Therefore, the radio base station does not discriminate head bits of received signals after the second received signal when the radio base station is supplied with the radio signals which are overlapped or serial. As a result, receiving characteristic of the received signals after the second received signal is deteriorated and operational characteristic of the bit synchronous circuit or the AFC circuit receives bad influence.
Also, modulation ripple is caused in the RSSI level due to modulation of received radio signal and change of the RSSI level is caused by change of an envelope due to fading. As a result, a slit (instant cutting) of a waveform of the RSSI level signal is caused when the RSSI level is near to the predetermined threshold level. In this event, malfunction of the bit synchronous circuit or the AFC circuit is caused by the slit of the waveform of the RSSI level signal.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a synchronizing system which is capable of certainly executing synchronizing operation even when the synchronizing system is supplied with radio signals which are overlapped or serial.
It is another object of this invention to provide a synchronizing system which is capable of preventing malfunction due to change of RSSI level.
Other objects of this invention will become clear as the description proceeds.
According to a first aspect of this invention, there is provided a synchronizing system comprising:
demodulating means receiving a received signal for demodulating the received signal to produce a demodulated signal having a CRC bit;
CRC bit end judging means connected to the demodulating means for judging an end of the CRC bit of the demodulated signal to produce a CRC bit end signal;
received signal level detecting means receiving the received signal for detecting a level of the received signal to produce a detected level signal having a detected level;
level comparing means connected to the received signal level detecting means for comparing the detected level of the detected level signal with a predetermined threshold level to produce a level compared result signal when the detected level is greater than the predetermined threshold level;
masking means connected to the CRC bit end judging means and to the level comparing means for masking, in a predetermined time interval, the level compared result signal when the masking means is supplied with both of the CRC bit end signal and the level compared result signal, the masking means producing a trigger signal when the masking means is supplied with the level compared result signal after the predetermined time interval; and
synchronizing means connected to the demodulating means and to the masking means for synchronizing the demodulated signal with the received signal by producing and supplying, in response to the trigger signal, a bit synchronous signal to the demodulating means.
According to a second aspect of this invention, there is provided a synchronizing system comprising:
demodulating means receiving a received signal for demodulating the received signal to produce a demodulated signal having a CRC bit;
CRC bit end judging means connected to the demodulating means for judging an end of the CRC bit of the demodulated signal to produce a CRC bit end signal;
received signal level detecting means receiving the received signal for detecting a level of the received signal to produce a detected level signal having a detected level;
level comparing means connected to the received signal level detecting means for comparing the detected level of the detected level signal with a predetermined threshold level to produce a level compared result signal when the detected level is greater than the predetermined threshold level;
triggering means connected to the CRC bit end judging means and to the level comparing means for producing a trigger signal when a predetermined time interval elapses when the triggering means is supplied with the level compared result signal and after the triggering means is supplied with both of the CRC bit end signal and the level compared result signal; and
synchronizing means connected to the demodulating means and to the triggering means for synchronizing the demodulated signal with the received signal by producing and supplying, in response to the trigger signal, a bit synchronous signal to the demodulating means.
According to a third aspect of this invention, there is provided a synchronizing system comprising:
demodulating means receiving a received signal for demodulating the received signal to produce a demodulated signal having a CRC bit;
CRC bit end judging means connected to the demodulating means for judging an end of the CRC bit of the demodulated signal to produce a CRC bit end signal;
received signal level detecting means receiving the received signal for detecting levels of the received signal to produce a detected level signal having detected levels;
level equalizing means connected to the received signal level detecting means for equalizing the detected levels of the detected level signal to produce an equalized detected level signal having an equalized detected level which is equal to an average level of the detected levels;
level comparing means connected to the level equalizing means for comparing the equalized detected level of the equalized detected level signal with a predetermined threshold level to produce a level compared result signal when the equalized detected level is greater
Chin Stephen
Jiang Lenny
NEC Corporation
Young & Thompson
LandOfFree
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