Synchronizing signal processing circuit

Details Synchronizing signal processing circuit Synchronizing signal processing circuit

1977-10-17

1979-08-28

Heyman, John S.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358158, H04N 508, H03K 500

Patent

active

041662504

ABSTRACT:
A synchronizing signal processing digital circuit adapted for integrated circuit manufacture for blanking equalization pulses from an input composite synchronization signal to obtain a synchronized horizontal-signal therefrom, which comprises D-type flip-flop having a clock input terminal to receive the composite sync signal and a D-input terminal to receive the composite sync signal and a D-input terminal fixed to a high level, a counter for counting input clock pulses of a frequency higher than that of the horizontal sync signal and applying a first pulse by counting a predetermined number of the clock pulses to a reset terminal of the D-type flip-flop, and a pulse generation circuit for applying a second pulse signal to set the counter in response to input clock pulse, whereby the synchronized signal free from the equalization pulses of the composite signal is produced with the output signal of the D-type flip-flop.

REFERENCES:
patent: 3593162 (1971-07-01), Patmore
patent: 3688037 (1972-08-01), Ipri
patent: 3991270 (1976-11-01), VAN Straaten et al.
patent: 4025952 (1977-05-01), Eckenbrecht
patent: 4070631 (1978-01-01), Nash et al.

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