Pulse or digital communications – Synchronizers – Frequency or phase control using synchronizing signal
Reexamination Certificate
1998-08-28
2001-12-18
Bocure, Tesfaldet (Department: 2731)
Pulse or digital communications
Synchronizers
Frequency or phase control using synchronizing signal
Reexamination Certificate
active
06332010
ABSTRACT:
BACKGROUND OF THE INVENTION
1 Field of the Invention
The present invention relates to a data recording/reproducing apparatus, and more particularly, to a synchronizing signal detecting circuit for detecting a synchronizing signal variably depending on the state of a system.
2. Discussion of the Related Art
Generally, a synchronizing pattern of bit streams predetermined by serial data during recording acts as a major factor in detecting a synchronizing signal. If the synchronizing pattern is damaged by breakage of a tape, degradation of a signal, error of drum rotation speed and the like, it is difficult to detect the synchronizing signal. In other words, for these reasons, error may occur in the synchronizing pattern and a data pattern. Thus, the data pattern may be detected in a synchronizing pattern form or the number of clocks between each synchronizing pattern may be inconsistent. As a result, it is not likely to detect the synchronizing signal.
In this respect, a serial method is widely used as a method for detecting a synchronizing signal. There is provided an example of the serial method in U.S. Pat. No. 4,275,466.
FIG. 1
shows configuration of the serial method according to the U.S. Pat. No. 4,275,466.
Referring to
FIG. 1
, serial input data S
0
from an input terminal
111
is input to a synchronizing pattern matching portion
115
through a shift register
114
. The synchronizing pattern matching portion
115
generates a detected synchronizing signal Si if the same signal as the synchronizing pattern is input.
A signal PG indicates that a head starts to read a track, and an input signal PR is a reference signal of the system. A signal SM which is a search mode setting signal becomes high if the PG signal is input, while becomes low if the Si signal is first generated after the PG signal is generated, so that the Si signal is acknowledged as the original synchronizing signal.
Furthermore, a synchronizing signal Sync is used as a clear signal of a counter
122
and is counted in the synchronizing block unit. The counter
122
counts the outputs of an OR gate
118
from 0 to N−1 repeatedly. The counted synchronizing signal S
1
is searched in an AND gate
123
which will be connected to an output terminal of the counter
122
. In other words, the counter
122
serves to forcibly generate the synchronizing signal by counting the outputs of the OR gate
118
. If the value of the counter
122
is generated after the first Si signal, the Si signal is acknowledged as the synchronizing signal by the AND gate
124
.
A signal CM, which is a check mode signal, becomes high if the detecting synchronizing signal Si differs from the counted signal Si, while becomes low if the output Sc of a comparator
135
is generated. In other words, the CM signal becomes high when the detected synchronizing signal Si is not detected at the position to be detected, while the CM signal becomes low if the Sc signal is generated. Therefore, if the Si signal, the CM signal, and the signal are all high, the Si signal is acknowledged as the final synchronizing signal.
However, the output of the counter
118
results in that the detected synchronizing signal Si and the counted synchronizing signal S
1
are all acknowledged as the synchronizing signal. In addition, if the value counted as much as the synchronizing block is identical with the synchronizing signal, the synchronizing signal is acknowledged. Therefore, in the case that the detected synchronizing signal Si and the forcible synchronizing signal S
1
occur almost simultaneously as the synchronizing signal is detected in error or inconsistency of the clock between the synchronizing blocks occurs, it is difficult to recognize the original synchronizing signal of the detecting synchronizing signal Si and the forcible synchronizing signal S
1
, thereby causing erroneous operation.
Furthermore, since the serial data are merely delayed without data alignment, error in data may occur even if the synchronizing signal is normally detected during data slip. This is involved in problems in data processing.
Since only one synchronizing signal pattern in advance is determined regardless of the state of the system and the synchronizing signal is acknowledged only if the synchronizing signal matches the synchronizing signal pattern accurately, it is likely to miss the synchronizing signal.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a synchronizing signal detecting circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a synchronizing signal detecting circuit for detecting a synchronizing signal by varying matching degree of a synchronizing signal pattern depending on the state of a system.
Another object of the present invention is to provide a synchronizing signal detecting circuit for designating in advance the position where a synchronizing signal will occur using a window and acknowledging only the synchronizing signal within the window as the synchronizing signal.
Other object of the present invention is to provide a synchronizing signal detecting circuit for detecting a synchronizing signal by varying a window area which designates in advance the position of the synchronizing signal.
Still another object of the present invention is to provide a synchronizing signal detecting circuit for acknowledging a final synchronizing signal only if identification (ID) is accurately detected in a synchronizing signal coming in next to the detected synchronizing signal.
Still other object of the present invention is to provide a synchronizing signal detecting circuit for converting input serial data to realigned parallel data and detecting a synchronizing signal so as to prevent erroneous operation from occurring due to clock inconsistency.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a synchronizing signal detecting circuit is characterized in that the state of a system is checked during reproducing data recorded in recording media, matching degree of a synchronizing signal pattern is determined depending on the state of the system, and a synchronizing signal is detected from input data in response to the determined matching degree.
In another aspect, a synchronizing signal detecting circuit of the present invention is characterized in that a window signal generator for generating a window signal is provided to acknowledge a synchronizing signal only if a detected synchronizing signal is within a window area and to remove the synchronizing signal detected in error. The window signal generator is characterized in that the window area is varied depending on the state of the system. The window signal generator is characterized in that a window signal is generated to the next synchronizing signal predict area if it is determined that the state of the system is poor. The window signal generator is characterized in that a window area is varied in a sub code area, a main data area, initial areas of the respective areas, and the other areas.
In other aspect, a synchronizing signal detecting circuit of the present invention is characterized in that an ID processor for detecting an ID signal is provided to acknowledge a final synchronizing signal only if the ID signal exists in a synchronizing signal coming in next to the detected synchronizing signal and to remove a synchronizing signal detected in error.
In still another aspect, a synchronizing signal detecting circuit of the present invention is characterized in that the state of
Bocure Tesfaldet
LG Electronics Inc.
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