Electricity: motive power systems – Plural – diverse or diversely controlled electric motors – Synchronizing or phasing control
Patent
1998-02-23
1999-11-23
Ip, Paul
Electricity: motive power systems
Plural, diverse or diversely controlled electric motors
Synchronizing or phasing control
318562, 318567, 36447411, 36447401, H02P 552, G05B 1918
Patent
active
059906383
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a method of synchronization in communication between devices in the field of numerical control devices, robot-controllers and their peripheral devices and similar industrial devices where it is vital that they operate in synchronization.
BACKGROUND ART
In a system consisting of a numerical control device (hereinafter referred to as CNC device), a robot-controller and its peripheral devices or similar industrial device, it is sometimes necessary to link a plurality of devices by means of serial communication for the purpose of ensuring that they operate in synchronization with one another. For instance, machine-tools which are driven and controlled by CNC devices must be synchronized in order to detect the current position of the individual feed shafts at the same point in time. Similarly, the individual shafts have to be moved in synchronization. Signals for the purpose of implementing synchronization of this sort are transmitted by way of serial communication.
For instance, FIG. 13 illustrates a system where two machines (master and slave) are connected by communication. One method of controlling the slave machine by synchronizing it with the aid of serial communication to the master machine involves emitting from the master machine to the slave machine a signal requesting transmission of a synchronizing signal with a predetermined cycle from a timer at a time which is to form the basis for synchronization, transmitting a packet (frame) on a transmission control circuit identifying it as a synchronizing signal, and transmitting this packet after conversion to a serial signal by means of a parallel-serial converter. Each time the reception control circuit of the slave machine receives this packet by way of a serial-parallel converter, it either operates its own internal sequencer or controls its own internal timer in such a manner as to make it conform to the timer of the master machine. This method is well known.
The packet which is transmitted from the master machine for the purpose of synchronization may be for exclusive use. Provided that a request for the transmission of data from the master machine is generated with synchronous timing, this data packet itself is sometimes treated as synchronization information. FIG. 14 illustrates an example of this packet. The slave machine may treat reception of either the whole packet or just the header section of the packet as a synchronization information.
When a packet is transmitted by serial communication, there is a discrepancy equivalent at least to the length of the serial data between the timing with which the transmitting side begins transmitting and that with which the receiving side finishes receiving the data.
FIG. 15 is a diagram which elucidates this discrepancy in timing for the example shown in FIG. 13. In FIG. 15 only the header section is treated as synchronization data (synchronizing signal). It is assumed that a request for transmission is generated cyclically in accordance with an internal timer in the master machine, and that now at a given time (reference time t0) such a request for transmission has been generated from the timer of the master machine. The transmission control circuit transmits a packet of the type illustrated in FIG. 14 to the parallel-serial converter, where it is converted into a serial signal and transmitted to the slave machine. There is a delay D1 from the time at which this signal requesting transmission was generated until the packet is transmitted to the transmission line. The reception of this packet by the slave machine entails further delays in the forms of the propagation time on the transmission line Dp and the time D2 required for synchronization. Inasmuch as the slave machine becomes aware of the arrival of the header section only after a fixed interval D3 from the completion of its reception, the synchronizing signal (header detection signal) generated by the slave machine is subject to a delay equivalent to the total of the delays (D1+Dp+D2+D3) from the t
REFERENCES:
patent: 4218705 (1980-08-01), Inaba et al.
patent: 4703431 (1987-10-01), Sako et al.
patent: 5390351 (1995-02-01), Di Giulio et al.
Aoyama Kazunari
Kubo Yoshiyuki
Fanuc Ltd.
Ip Paul
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