Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
Reexamination Certificate
2006-10-31
2009-02-10
Kim, Kenneth S (Department: 2111)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
C712S023000, C712S217000
Reexamination Certificate
active
07490225
ABSTRACT:
Synchronized register renaming between a master processor and a coprocessor that receives operations from the master enables efficient implementation of register renaming and operation execution in the processors. An ideal and an external register allocation map are implemented in the coprocessor. When registers are no longer allocated according to the ideal allocation map and the registers are currently allocated according to the external allocation map, the registers are deallocated in the external map and the number of freed registers is reported to the master. The master increments a free register credit count accordingly, and decrements the credit count by one for each operation issued to the coprocessor. An operation is not issued to the coprocessor unless at least a register is free according to the credit count. The master also throttles coprocessor operation issue based on a credit count corresponding to free scheduler entries available in the coprocessor.
REFERENCES:
patent: 4992938 (1991-02-01), Cocke et al.
patent: 5708837 (1998-01-01), Handlogten
patent: 5748468 (1998-05-01), Notenboom et al.
Favor John Gregory
Nelson Christopher P.
Kim Kenneth S
Osha • Liang LLP
Sun Microsystems Inc.
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