Synchronizing flip-flop circuit configuration

Details Synchronizing flip-flop circuit configuration Synchronizing flip-flop circuit configuration

1988-08-15

1990-06-12

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307480, 307279, 307452, 307443, H03K 3284, H03K 326

Patent

active

049335715

ABSTRACT:
A synchronizing flip-flop circuit configuration for synchronizing data includes an input and an output of the synchronizing flip-flop circuit configuration. A first transfer gate, connected to the input of the synchronizing flip-flop circuit configuration, is controlled by a first clock signal. A second transfer gate connected between the first transfer gate and the output of the synchronizing flip-flop circuit configuration is controlled by a second clock signal being inverted with respect to the first clock signal. A first series-connected inverter pair is connected between the first transfer gate and the output of the synchronizing flip-flop circuit configuration. At least one second inverter series-connected inverter pair is connected in series with the first inverter configuration between the first transfer gate and the output of the synchronizing flip-flop circuit configuration, thereby preventing occurrence of meta-stable conditions between data to be synchronized.

REFERENCES:
patent: 3930169 (1975-12-01), Kuhn, Jr.
patent: 4224531 (1980-09-01), Ebihara et al.
patent: 4667339 (1987-05-01), Tubbs et al.
patent: 4785200 (1988-11-01), Huntington
Mead, Carver A. and Lynn A. Conway, "Introduction to VLSI Systems", (Addison-Wesley Publishing Co., Inc. Philippines 1980) 3rd Ed., pp. 236-242.

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