Synchronizing digital video inputs

Television – Flutter or jitter correction

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Details

370102, 370108, 375372, 348715, H04N 1100, H04N 700

Patent

active

054520100

ABSTRACT:
A system for synchronizing asynchronous video signals with a reference signal for input to a digital video processing system has a first-in, first-out (FIFO) buffer for each input signal that writes the digitized video signal into the FIFO under control of an input clock signal derived from the digitized video signal, and reads the digitized video signal from the FIFO under control of the reference signal. An input state machine monitors the digitized video signal at the input and the occupancy of the FIFO to provide a write enable signal to the FIFO so long as the FIFO is not in danger of overflowing. An output state machine monitors the digitized video signal at the output and the occupancy of the FIFO to provide a read enable signal to the FIFO so long as the FIFO is not in danger of underflowing. When the FIFO is in danger of overflowing, the write enable signal is disabled during the blanking interval of the digitized video signal for a pre-determined number of pixels; and when the FIFO is in danger of underflowing, the read enable signal is disabled during the blanking interval of the digitized video signal for a pre-determined number of pixels.

REFERENCES:
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patent: 4945548 (1990-07-01), Lannarone et al.
patent: 5272728 (1993-12-01), Ogawa
patent: 5359366 (1994-10-01), Ubukata et al.
"1990-91 Specialized Memories Data Book" Integrated Devices Technology, Inc., 1990.

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