Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1998-10-26
2002-03-19
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S144000, C375S362000
Reexamination Certificate
active
06359479
ABSTRACT:
BACKGROUND
The present invention relates generally to electronic circuits, and more particularly to methods and apparatus for transferring data between two distinct clock domains in a digital circuit.
Synchronization of electrical devices in a digital electronic circuit is typically performed using a clock signal. A central clock source provides as an output the clock signal. The clock signal in turn may be coupled to each device in the electronic circuit. Flip flops, latches and the like are commonly available with clock inputs for receiving a clock signal. The operation of each device may be triggered based on the clock signal.
Electrical circuit applications often require the transfer of data from one circuit to another. The transferring circuit, often referred to as a driver, transfers data along a data link to a receiving circuit, often referred to as a receiver.
The transfer of data between circuits in an electrical device, often requires some form of synchronization. Synchronization may be achieved by operating devices in each circuit on the same clock signal, or by providing clocking signals along with data as the data is transferred between the respective circuits.
In certain digital circuit applications, two circuits within a device may be required to be operated in distinct clock domains. That is, each circuit may make use of a distinct clock signal to trigger operations in the respective circuit. For example, data may be received at an input gate (receiver) on one circuit board controlled by a first clock signal CLK
1
from an output gate (transmitter) on second circuit board controlled by a second distinct clock signal CLK
2
.
Data may be required to be transferred between the two circuits, where each operates in a distinct clock domain. Where the two clock signals have different frequencies, data transfer is problematic. Even if the two clock signals are operated at the same frequency (the two circuits are synchronous), the arbitrary phase relationship between the signals may result in metastability issues. A metastability failure may occur at a receiver, operating in a first clock domain, due to the difference in phase relationship between the received data, passed from a driver operating in a distinct second clock domain, and the local clock.
SUMMARY OF THE INVENTION
In general, in one aspect, the invention provides a method for transferring data between a driver and a receiver operating in two distinct clock domains under the control of first and distinct second clock signals. The method includes transferring data out from the driver at an active edge of the first clock signal. A delay after the active edge of the first clock signal that data may be unstable is determined. The reading of data received from the driver at the receiver is delayed until an active edge of the first clock signal is received that is generated after the delay has expired.
Aspects of the invention include numerous features. The frequency of the second clock signal can be an integer multiple of the frequency of the first clock signal. The reading of data can include determining a best edge that is farthest from a metastable region. The best edge can be selected as an edge that is closest to a center of a valid data region.
In another aspect, the invention provides a data interface for transferring data between circuits operating in two distinct clock domains and includes a driver including a latch having an input port and an output port operable to transfer an input signal received at the input port to the output port on an active edge of a clock signal, receiver including a second latch having an input port and an output port operable to transfer the input signal received at the input port to the output port on an active edge of the second clock signal. The frequency of the second clock signal is an integer multiple of the frequency of the first clock signal. The receiver includes a delay circuit triggered by the active edge of the first clock signal and operable to produce a delayed signal active a predetermined time after the second clock signal is active, and a selector coupled to the delay circuit for selecting an appropriate edge of the second clock signal that is active after receipt of the delayed signal. The selector is coupled to the second latch and operable to trigger the read of data from the driver on the appropriate edge.
In another aspect, the invention provides a data interface for transferring data between circuits operating in two distinct clock domains under the control of a first and distinct second clock signals where the frequency of the second clock signal is an integer multiple of the frequency of the first clock signal. The data interface includes a driver including a latch having an input port and an output port operable to transfer an input signal received at the input port to the output port on an active edge of the second clock signal. The interface includes a receiver including a second latch having an input port and an output port operable to transfer the input signal received at the input port to the output port on an active edge of the first clock signal. The receiver includes a multiplexor, a delay element and a synchronization circuit. The multiplexor includes an input coupled to the output port of the latch in the driver, an output coupled to the input port of the second latch and an enable port for enabling the transfer of data through the multiplexor. The delay circuit is triggered by the active edge of the second clock signal and operable to produce a delay signal active a predetermined time after the second clock signal is active. The synchronization circuit is operable to receive the delay signal and generate an enable signal that is coupled to the enable port of the multiplexor.
Among the advantages of the invention are one or more of the following. Successful synchronous data transfers between two circuits operating in distinct clock domains is achieved by adjusting the data arrival time as a function of the phase relationship between the two distinct clocks. The adjustment is optimally performed in order to accommodate further variations in the phase relationship between the two clock signals. The present invention has applicability to data transfers between two distinct clock domains across circuit boards, integrated circuits or within an integrated circuit. Successful synchronous data transfers may be achieved without requiring the derivation of the receiving domain clock from the received data. Data signals may be received at a first circuit controlled by a first clock signal in a first clock domain from a second circuit controlled by a second distinct clock signal in a second clock domain with a minimum probability of a metastable failure.
Other advantages and features will be apparent from the following description and claims.
REFERENCES:
patent: 5185768 (1993-02-01), Ferraiolo et al.
patent: 5256912 (1993-10-01), Rios
patent: 5834956 (1998-11-01), Pathikonda et al.
patent: 5999023 (1999-12-01), Kim
patent: 0 678 990 (1995-10-01), None
patent: 0798 630 (1997-10-01), None
Callahan Timothy P.
Juniper Networks, Inc.
Nguyen Linh
LandOfFree
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