Synchronizing clock pulse generator for logic derived clock sign

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing

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327162, 327172, H03K 1722, H03L 700

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active

059125721

ABSTRACT:
A programmable device includes a circuit for generating an asynchronous logic derived clock signal from one or more of a number of input signals. Circuits for synchronizing the asynchronous logic derived clock signal to a reference clock signal are coupled to the circuit for generating. The circuits for synchronizing generate a synchronized logic derived clock signal from the asynchronous logic derived clock signal and the reference clock signal. The synchronized logic derived clock signal has a fixed duration logic HIGH interval for variable duration logic HIGH intervals of the input logic signals from which the synchronized logic derived clock signal is created. Further, the programmable device includes circuit for suspending a clock signal. In one embodiment, an asynchronous logic derived clock signal is generated and synchronized with a synchronous clock signal provided to the programmable device to produce a synchronized logic derived clock signal. The synchronized logic derived clock signal is logically combined with the synchronous clock signal to produce a suspended clock signal.

REFERENCES:
patent: 4004090 (1977-01-01), Goto et al.
patent: 4973860 (1990-11-01), Ludwig
patent: 5522048 (1996-05-01), Offord
patent: 5764710 (1998-06-01), Cheng et al.

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