Synchronizing circuit provided with hysteresis phase comparator

Details Synchronizing circuit provided with hysteresis phase comparator Synchronizing circuit provided with hysteresis phase comparator

2007-01-23

2007-01-23

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S003000, C327S151000, C331S025000

Reexamination Certificate

active

10746454

ABSTRACT:
A synchronizing circuit includes a phase comparator having hysteresis characteristics and a dead zone, and configured to generate a frequency division ratio control signal based on a phase difference between a first clock and a second clock. The circuit further includes a variable frequency divider configured to generate a fourth clock by subjecting a third clock to frequency division at a frequency division ratio set in accordance with the frequency division ratio control signal, and a clock generator configured to subject the fourth clock supplied from the variable frequency divider to frequency division at a predetermined frequency division ratio, and generate the second clock such that the second clock synchronizes with transfer data which is supplied from an outside of the synchronizing circuit.

REFERENCES:
patent: 3217267 (1965-11-01), Loposer
patent: 4612515 (1986-09-01), Ohkawa et al.
patent: 4970475 (1990-11-01), Gillig
patent: 5699387 (1997-12-01), Seto et al.
patent: 6049233 (2000-04-01), Shurboff
patent: 6771096 (2004-08-01), Meyers et al.
Donald G. Troha, “Digital Phase-Locked Loop Design Using SN54/74LS297,” Texas Instruments, pp. 1-15, Mar. 1997.

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