Synchronizing circuit of two clock signals

Details Synchronizing circuit of two clock signals Synchronizing circuit of two clock signals

1990-08-27

1992-02-04

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307481, H03K 513, H03K 19096

Patent

active

050862367

ABSTRACT:
There is disclosed a synchronizing circuit for synchronizing a first clock signal to a second clock signal. The synchronizing circuit includes an edge-triggered set-reset latch and a delay circuit. A subclock generator generates first and second subclock signals from a synchronizing clock to control the delay circuit so that the synchronized signal at the output of the circuit is exactly one full cycle period of the synchronizing clock signal.

REFERENCES:
patent: 4417158 (1983-11-01), Ito et al.
patent: 4691122 (1987-09-01), Schnizlein et al.
patent: 4691124 (1987-09-01), Ledzius et al.
patent: 4758737 (1988-07-01), Hirano
patent: 4973860 (1990-11-01), Ludwig

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