Synchronizing circuit in a plesiochronous digital signal multipl

Details Synchronizing circuit in a plesiochronous digital signal multipl Synchronizing circuit in a plesiochronous digital signal multipl

1985-05-01

1987-05-26

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370102, 375112, H04J 306

Patent

active

046690808

ABSTRACT:
The invention relates to a synchronizing circuit for synchronizing one of N digital plesiochronous signals with a local clock signal with a view to transcoding and justifying the plesiochronous signal in a multiplexer. More particularly, the invention is directed to the regeneration of a timing signal relative to the plesiochronous signal by use of logic circuits permitting integration. A timing signal generating device comprises a first logic circuit for periodically deleting a pulse in the local clock signal in terms of a phase-shift between the regenerated timing signal and the clock signal to produce an intermediate clock signal having a periodically deleted pulse comparatively with the local clock signal, and a second logic circuit for dividing the intermediate clock signal in frequency by 2N to produce the regenerated timing signal.

REFERENCES:
patent: 3830981 (1974-08-01), Gruber et al.
patent: 3916084 (1975-10-01), Toole
patent: 3919647 (1975-11-01), Haass
patent: 4002844 (1977-01-01), Doussoux
patent: 4063040 (1977-12-01), Fontanes et al.
patent: 4076964 (1978-02-01), Henrion et al.
patent: 4408333 (1983-10-01), Fujii
A. Aveneau et al, "Possibilities Given by the Use of Large Scale Integrated Ckts. in the 2048-8448 kbit/s Multiplexer-Demultiplexer", IEEE, Mar. 1976, pp. A2.1-A2.4.

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