Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-05-26
2001-03-27
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S215000
Reexamination Certificate
active
06208188
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a synchronizing circuit and, more particularly, to a synchronizing circuit which receives an asynchronous input signal in synchrony with an internal clock signal to supply the asynchronous input signal as a synchronous signal to an internal circuit such as a computer system using the internal clock signal.
(b) Description of the Related Art
Synchronizing circuits are widely used in a semiconductor integrated circuit such as implementing a computer system operating on an internal clock signal.
FIG. 1
shows a conventional synchronizing circuit including a D-flipflop (D-F/F). The D-F/F
11
is of a master-slave type which includes a first stage master latch
12
and a second stage slave latch
13
, and latches an asynchronous input data “D” in synchrony with a clock signal CLK used in the internal circuit implementing a computer system.
The master latch
12
includes a first gate block
14
which includes a 2-input NAND gate
17
and a two-input OR gate
16
having an output connected to the first input of NAND gate
17
, and a second gate block
15
which includes a two-input NAND gate
19
and a two-input OR gate
18
having an output connected to the first input of NAND gate
19
. The output of NAND gate
17
is connected to the second input of NAND gate
19
, whereas the output of NAND gate
19
is connected to the second input of NAND gate
17
. OR gate
16
receives clock signal CLK and inverted data Db through an inverter
26
, whereas OR gate
18
receives clock signal CLK and noninverted data D.
The slave latch
13
includes a third gate block
20
which includes a two-input NOR gate
23
and a two-input AND gate
22
having an output connected to the first input of NOR gate
23
, and a fourth gate block
21
which includes a two-input NOR gate
25
and a two-input AND gate
24
having an output connected to the first input of NOR gate
25
. AND gate
22
receives clock signal CLK and an output Qm from NAND gate
17
of the first gate block
14
, whereas AND gate
24
receives clock signal CLK and an output Qmb from NAND gate
19
of the second gate block
15
. NOR gate
23
outputs data Qb and OR gate
21
outputs data Q to the internal circuit not shown.
It is known that the D-F/F of
FIG. 1
exhibits a metastable state. This will be described with reference to timing charts of
FIGS. 2 and 3
in addition to FIG.
1
. As shown in
FIG. 2
, the second gate block
15
of the master latch
12
receives a low level of non-inverted data D at a low level of the clock signal CLK during period T
2
, to output an inverted data Qmb made from the non-inverted data D. On the other hand, the first gate block
14
receives a high level of inverted data Db at the low level of the clock signal CLK during period T
2
to output non-inverted data Qm made from the inverted data Db. The data Qm and Qmb are latched when the clock signal CLK rises from the low level to a high level at the rising edge “a” of the clock signal, and maintained during the high level of the clock signal CLK during period T
3
.
The third gate block
20
of the slave latch
13
receives the output Qm from NAND gate
17
at the high level of the clock signal CLK during period T
3
, to output inverted data Qb, whereas the fourth gate block
21
receives the output Qmb at the high level of the clock signal CLK during period T
3
, to output non-inverted data Q. The slave latch
13
latches the data Q and Qb when the clock signal falls from the high level to a low level, and maintains the data Q and Qb at the low level of the clock signal CLK during period T
3
. Thus, input data D and Db are effectively latched at the rising edge “a” at the end of period T
2
by the D-F/F
11
, to be output as data Q and Qb at next period T
3
. This is due to the ordinary timing of the input data D with respect to the clock signal CLK.
On the other hand, if data D and Db falls and rises, respectively, at a rising edge “b” of the clock signal CLK, as shown in
FIG. 3
, the master latch
12
shifts to and stays while in a metastable state wherein the internal of the mater latch is not fixed during a first half of next period T
2
. The metastable state does not allow the master latch
12
to provide effective outputs, as shown by hatching “e” and “f” of the outputs Qm and Qmb. Thus, the slave latch
13
of the next stage also shifts to and stays while in a metastable state as shown by hatching of outputs Q and Qb during period T
2
. Although it is assured that the data D and Db are latched at the next rising edge of the clock signal CLK, the metastable state of the D-F/F requires a complex timing design for the computer system including the synchronizing circuit.
Referring to
FIG. 4
, there is shown another conventional D-F/F
11
A wherein the master latch
12
A includes a first gate block
20
A which is similar to the third gate block
20
of
FIG. 1 and a
second gate block
21
A which is similar to the fourth gate block
21
of
FIG. 1
, and the slave latch
13
A includes a third gate block
14
A which is similar to the first gate block
14
of
FIG. 1 and a
fourth gate block
15
A which is similar to the second gate block
15
of FIG.
1
. In the D-F/F
11
A of
FIG. 4
, the master latch
12
A receives data D and Db at a high level of the clock signal CLK to output data Qm and Qmb, then latches the data at a falling edge of the clock signal CLK, and maintains the data at a next low level of the clock signal CLK.
The slave latch
13
A receives data Qm and Qmb at the low level of the clock signal CLK to output data Q and Qb, then latches the data at a next rising edge of the clock signal CLK, and maintains the data at a next high level of the clock signal CLK.
In the another conventional D-F/F
11
A, the D-F/F
11
A also exhibits metastable states if data D and Db change at a falling edge of a clock pulse of the clock signal CLK.
In recent computer systems, the clock cycle of the clock signal is more and more reduced. The metastable state described above generally continues for several tens of nanoseconds, thereby increasing power dissipation of the computer system. In addition, the metastable state requires complex design for signal timing in waiting of transition to a stable state, and thus restricts the operational speed of the computer system, although the frequency itself of the occurrence of the metastable state is comparatively low.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a synchronizing circuit capable of reducing the time length of the metastable state with a relatively simple structure, thereby reducing power dissipation of the synchronizing circuit and improving operational speed of the semiconductor integrated circuit.
The present invention is directed to a synchronizing circuit for latching an asynchronous input data to output a synchronous output data in synchrony with a clock signal. The synchronizing circuit includes a first latch section having a first node, a second node, and a first capacitor connected between the first node and the second node for capacitive coupling therebetween, the first capacitor assisting a signal transition of the second node by using electric energy of a signal transition of the first node.
In accordance with the synchronizing circuit of the present invention, the capacitor assisting the signal transition of the second node reduces the time length of the metastable state of the synchronizing circuit, thereby reducing power dissipation and improving operational speed of the synchronous circuit such as used in a computer system.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.
REFERENCES:
patent: 4560954 (1985-12-01), Leach
patent: 5111489 (1992-05-01), Tanaka et al.
patent: 5332931 (1994-07-01), Crispie et al.
patent: 5367489 (1994-11-01), Park et al.
patent: 5821780 (1998-10-01), Hasegawa
Hutchins, Wheeler & Dittmar
NEC Corporation
Nguyen Linh
Tran Toan
LandOfFree
Synchronizing circuit for receiving an asynchronous input... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Synchronizing circuit for receiving an asynchronous input..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronizing circuit for receiving an asynchronous input... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2544939