Synchronizing circuit for dividing a frequency of a clock signal

Details Synchronizing circuit for dividing a frequency of a clock signal Synchronizing circuit for dividing a frequency of a clock signal

1995-06-19

1997-01-21

Wambach, Margaret Rose

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327151, 327295, H03K 104

Patent

active

055962947

ABSTRACT:
A synchronizing circuit has a first signal generating unit for dividing a control signal to obtain a first signal having a first frequency, a second signal generating unit for dividing the control signal to obtain a second signal having a second frequency, a third signal generating unit for dividing the control signal to obtain a third signal having a third frequency and synchronized with the second signal, and a synchronizing signal generating unit for generating a synchronizing signal which is adapted to synchronize the first signal with the second and third signals in accordance with a logical operation on the first, second and third signals. With this arrangement, the internal clock signals can be synchronized without using a reset signal. Consequently, neither wiring for supplying the reset signal nor a circuit for generating the reset signal are necessary.

REFERENCES:
patent: 3740660 (1973-06-01), Davies, Jr.
patent: 3896388 (1975-07-01), Hatsukano et al.
patent: 4463440 (1984-07-01), Nishiura et al.

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