Synchronizing circuit

Details Synchronizing circuit Synchronizing circuit

1999-07-16

2001-04-24

Pham, Chi (Department: 2631)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S357000

Reexamination Certificate

active

06222893

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a synchronizing circuit, and especially to a synchronizing circuit for synchronizing an input signal with an asynchronous clock.
BACKGROUND OF THE INVENTION
In an interface of a computer, the maximum clock frequency is determined on the basis of a standard required to the outside, and it sometimes occurs that a communication or a process cannot be performed without comforting to the aforementioned standard. However, in the inside of the apparatus, it is possible to increase the clock frequency so long as circuit elements, such as ICs, can follow, and a speed of a data process can be increased in proportion to the clock frequency. In such a case, it is indispensable to synchronize a data and a control signal changing in accordance with a clock of the interface with a system clock, and the synchronizing circuit is used for this purpose.
A control signal changing by “1” every clock, such as a pointer of a FIFO (First In First Out) type or a counter, is sometimes desired to be synchronized. For example, as a method for synchronizing datas composed of plural bits, a circuit of asynchronous FIFO type, in which there is a difference ina clock between the write and read circuits, is used. In such a case, it is necessary to certainly synchronize the pointers of the write and read circuits.
The simplest structure of the synchronizing circuit is that a data to be synchronized is inputted to a flip-flop circuit (a F/F circuit, hereinafter), the F/F circuit is made to operate by applying a clock signal thereto, and a synchronized data is outputted.
According to the conventional synchronizing circuit, a following problem occurs.
In case that a pointer represented by a ordinary binary code is synchronized, if the data is latched by the synchronizing circuit (the F/F circuit) on a course of a transition of the data, it may well be that the data will be regarded as a quite different one, because there is a difference in delay between the respective bits. For example, in case that a signal composed of three bits is latched on a course of a transition from “011” to “100”, if bit
2
of “100” is latched after the transition and bits
1
and
0
are latched before the transition, the output data of the synchronizing circuit becomes “111”, which is quite different from “011” and “100”. Moreover, since “111” may occur at the time of normal operation, the error of synchronizing cannot be detected.
Next, in case that a pointer of a one hot type is latched on the course of the transition, the number of “1”s is sometimes regarded as 0 or 2. For example, in case that a pointer composed of five bits is latched on a course of a transition form “00010” to “00100”, if bit
1
or
2
delays, it may well be that the output data of the synchronizing circuit will be regarded as “00110” or “00000”. However, in such a case, it can be clearly recognized that an error occurs in the synchronizing circuit. In order to cope with such a situation, the synchronizing circuit must be provided with a device for processing an irregularly synchronized data, hence much labor is required for a circuit design, a structure becomes complicated, and an increasing in cost is inevitable.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a synchronizing circuit which prevents an occurrence of an unexpected output data caused by latching a data to be synchronized on a course of a transition thereof.
According to the feature of the invention, a synchronizing circuit comprises:
A synchronizing circuit, which synchronizes a binary data composed of n bits and changing synchronizing with a first clock of a first frequency with a second clock of a second frequency, comprising:
a signal-generating circuit for generating a binary data composed N (N≧-n) bits by encoding the binary data composed of n bits,
a latch circuit for latching the binary data composed of N bits synchronizing with the second clock, and
a decoding circuit for decoding the binary data composed of N bits latched by the latch circuit into a binary code composed of n bits.


REFERENCES:
patent: 5016258 (1991-05-01), Tanaka et al.
patent: 5905766 (1999-05-01), Nguyen
patent: 10-13398 (1998-01-01), None
patent: 10-164037 (1998-06-01), None

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