Synchronizing arrangement

Details Synchronizing arrangement Synchronizing arrangement

1983-07-14

1985-02-19

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

H04J 306

Patent

active

045009929

ABSTRACT:
A time division multiplex signal of a high order with a frame code word which occurs block-wise is distributed between a plurality of channels in a demultiplexer and is supplied to the inputs of a synchronizing arrangement. The transmission path of the synchronizing arrangement comprises memories and a channel distributor. The channel distributor is controlled by the first memory by way of a decoder, further memories, and a coder in a single step. A logic linking arrangement and a frame counter permit resynchronization only when the frame code has failed to appear four times in succession. The synchronizing arrangement facilitates high-speed synchronization at bit rates of 140 Mbit/s and 565 Mbit/s, and also permits construction in accordance with emitter-coupled logic technology.

REFERENCES:
patent: 3593044 (1971-07-01), McNeilly
patent: 3699261 (1972-10-01), Tomozawa
patent: 4371962 (1983-02-01), Zeitraeg
patent: 4404680 (1983-09-01), Perkins
CCITT "Yellow" Book, vol. 111, pp. 219-220 (Fascicle 111.3 Rec. G.992, Sec. 3.4).

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