Synchronizing and processing of memory access operations in mult

Details Synchronizing and processing of memory access operations in mult Synchronizing and processing of memory access operations in mult

1989-02-03

1992-12-29

Gossage, Glenn

Boots, shoes, and leggings

3642468, 3649692, 365195, G06F 1200, G06F 1318

Patent

active

051758377

ABSTRACT:
All monitoring and control of locked memory access requests in a multiprocessing computer system is handled by a system control unit (SCU) which controls the parallel operation of a plurality of central processing units (CPUs) and I/O units relative to a common main memory. Locking granularity is defined at the level of individual cache blocks for the CPUs, and the cache blocks also represent the unit of memory allocation in the computer system. The SCU is provided with a lock directory defined by a plurality of lock bits so that addresses in the same block of memory are mapped to the same location in the lock directory. Incoming lock requests for a given memory location are processed by interrogating the corresponding lock bit in the lock directory in the SCU by using the associated memory address as an index into the directory. If the lock bit is not set, the lock request is granted. The lock bit is subsequently set and maintained in that state until the unit requesting the lock has completed its memory access operation and sends an "unlock" request. If the interrogated lock bit is found to be set, the lock request is denied and the requesting port is notified of the denial. Fairness for the processing of denied lock requests is insured by a reserve list onto which denied requests are sequentially positioned on a first-come-first-served basis.

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