Synchronizing a prediction RAM

Details Synchronizing a prediction RAM Synchronizing a prediction RAM

1996-05-24

1997-07-15

Beausoliel, Jr., R. W.

Boots, shoes, and leggings

39518209, 36494392, 3642683, G06F 1100

Patent

active

056490976

ABSTRACT:
A fault tolerant processing system including a prediction RAM employs a Lock Step Compare routine. The method developed allows the processing system to recover from single event upsets. In initialization, the branch prediction RAM is set to a known value. An engineering balance is achieved by adding logic to detect a branch RAM error and incurring the delay of re-initializing the entire RAM only when a RAM error has been detected.

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