Synchronizer for time division multiplexed data

Details Synchronizer for time division multiplexed data Synchronizer for time division multiplexed data

1985-12-23

1988-04-26

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

370100, 375116, H04J 306, H04L 700

Patent

active

047409622

ABSTRACT:
A circuit which finds a synchronization pattern and provides synchronized data from incoming time division multiplexed data is disclosed. The incoming data includes an incoming clock signal used in saving the incoming data in a FIFO memory. A local clock, which is isolated from the incoming clock but exhibits substantially the same rate as the incoming clock, retrieves output data from the FIFO memory. A series of bits from the output data which includes bits having relative bit positions that correspond to the bit positions of the synchronization pattern are examined for the occurrence of the synchronization pattern. If the synchronization pattern is not found, a dummy bit is added to the incoming data stream. The added dummy bit causes the quantity of data stored in the FIFO memory to increase the delays the output data by one bit relative to the output data prior to the addition of the dummy bit. The above described process repeats until synchronization is achieved.

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