Synchronizer circuit with dual input

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307279, 307269, 307443, 307582, 328201, H03K 1730, H03K 19096, H03K 17693

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active

045448515

ABSTRACT:
A digital synchronizer circuit including an input to receive an asynchronous level and a second input to receive an ansynchronous pulse. Both inputs are connected to the synchronizer input circuitry which will provide a level output for either type of input signal. This circuitry is connected to the remainder of the digital synchronizer which includes a latch connected to the level input and a level sensitive circuit connected to the output of the latch. The latch is constructed to provide a rapid transition between a logic "0" and "1". In addition, the latch is periodically cleared. The level sensitive circuit provides a propagation barrier to any metastable state that may be present in the latch. However, the level sensitive circuit is also constructed for rapid transition from a logic "0" to a logic "1" when such a state occurs within the latch. An additional latch is connected in a further embodiment to provide additional reliability of the synchronizer circuit. The second latch is a two inverter latch with refresh for a three quarter of a machine cycle to allow any transient conditions within the latch to dampen out.

REFERENCES:
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patent: 4011465 (1977-03-01), Alvarez, Jr.
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patent: 4282489 (1981-08-01), De Rienzo
patent: 4317053 (1982-02-01), Shaw et al.
patent: 4380736 (1983-04-01), Pfaff
Chaney et al., "Beware the Synchronizer", COMPCON-72, IEEE Computer Society Conference, San Francisco, Ca., Sep. 12-14, 1972.
Elineau et al., "A New JK Flip-Flop for Synchronizers", IEEE Transactions on Computers, vol. C-26, No. 12, 12-1977, pp. 1277-1279.
Chaney et al., "Anomalous Bahavior of Synchronizer and Arbiter Circuits", IEEE Transactions on Computers, vol. C-22, No. 4, 4-1973, pp. 421-422.
Marino, "The Effect of Asynchronous Inputs on Sequential Network Reliability", IEEE Transactions on Computers, vol. C-26, No. 11, 11-1977, pp. 1082-1090.

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