Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1981-07-20
1984-09-04
Anagnos, Larry N.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307269, 307362, 307582, 307279, 328201, H03K 1730, H03K 19095, H03K 3286
Patent
active
044699646
ABSTRACT:
A digital synchronizer includes a latch connected to a level sensitive circuit. The latch is constructed to provide a rapid transition between logic "0" and logic "1". In addition, the latch is periodically cleared. The level sensitive circuit provides a propagation barrier to any metastable state that may be present in the latch. However, the level sensitive circuit is also constructed for rapid transition from logic "0" to logic "1" when such a state occurs within the latch. An additional latch is connected in a further embodiment to provide additional reliability of the synchronizer circuit. The second latch is a two inverter latch with refresh for 3/4 of a machine cycle to allow any transients conditions within the latch to dampen out.
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Chaney et al., "Beware the Synchronizer" Compcon-72, IEEE Computer Society Conference, San Francisco, Ca., Sep. 12-14, 1972.
Elineau et al., "A New J-K Flip-Flop for Synchronizers", IEEE Transactions on Computers, vol. C-26, No. 12, 12-1977, pp. 1277-1279.
Chaney et al., "Anomalous Behavior of Synchronizer and Arbiter Circuits," IEEE Transactions on Computers, vol. C-22, No. 4, 4-1973, pp. 421-422.
Marino, "The Effect of Asynchronous Inputs on Sequential Network Reliability," IEEE Transactions on Computers, vol. C-26, No. 11, 11-1977, pp. 1082-1090.
Carey James
Guttag Karl M.
Anagnos Larry N.
Hudspeth David R.
Merrett N. Rhys
Sharp Mel
Texas Instruments Incorporated
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