Synchronized selectable rate clocking system

Details Synchronized selectable rate clocking system Synchronized selectable rate clocking system

1984-04-02

1985-12-24

Heyman, John S.

Pulse or digital communications

Repeaters

Testing

328 55, 328155, 375117, H04J 306, H03L 700

Patent

active

045609390

ABSTRACT:
A data processing system is provided with multiple system clock sources operating at different frequencies for selectively and synchronously driving a plurality of clock pulse generators. The clock pulse generators include four-stage ring counters which may be controlled to produce either four or eight phase clocking signals. When a change is to be made from one system clock source to another, the clock pulse generators are stopped. A phase capture register stores an indication of the last phase generated. While the clock pulse generators are stopped, the change over to the new system clock source is made. The clock pulse generators are restarted at a first time or a second, later time depending upon whether the stored phase indication indicates that the clock pulse generators were stopped at one of phases 5-8 or one of phases 1-4.

REFERENCES:
patent: 3787749 (1974-01-01), Uchida et al.
patent: 3938144 (1976-02-01), Pederson et al.
patent: 4017683 (1977-04-01), Pederson et al.
patent: 4419629 (1983-12-01), O'Brien
patent: 4475085 (1984-10-01), Yahata et al.

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