Synchronized pulse width modulator

Details Synchronized pulse width modulator Synchronized pulse width modulator

2002-08-29

2003-12-16

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S155000, C341S156000

Reexamination Certificate

active

06664908

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to delta-sigma analog-to-digital converter devices and methods, and in particular to means for measuring the duty cycle of a delta-sigma analog-to-digital converter device.
BACKGROUND OF THE INVENTION
A device for converting an analog signal to a digital signal for processing by a digital computer is an analog-to-digital (A/D) converter that uses a pulse width modulator type quantizer, which produces a pulse train having a duty cycle that is proportional to the input analog signal level, followed by means to measure the duty cycle over some time period of interest. A known method for implementing a pulse width modulator is the delta-sigma (&Dgr;-&Sgr;) quantizer, detailed in FIG.
3
and discussed below.
Delta-sigma analog-to-digital (&Dgr;-&Sgr; A/D) converters are a class of A/D converters characterized by use of the extremely simple &Dgr;-&Sgr; quantizer design. The quantizer within a &Dgr;-&Sgr; A/D converter provides an output signal having only one bit of resolution. To achieve higher resolutions, many sequential output samples from the quantizer are averaged or processed by other digital means. The primary advantage of &Dgr;-&Sgr; A/D converters is their analog simplicity which makes them exceptionally linear, small, and insensitive to component tolerance variations so that they are easy to integrate within a mostly digital integrated circuit.
Prior art &Dgr;-&Sgr; A/D converters are characterized by feeding a source of analog information into a &Dgr;-&Sgr; A/D quantizer that converts the analog data into a “density” modulated serial digital data stream, and subsequent digital signal processing of that data to arrive at a meaningful output. The &Dgr;-&Sgr; A/D quantizer includes one or more stages of analog integration, which corresponds to the “order” of the quantizer. This is followed by a digital delay stage, typically, a latch, which provides the output from the quantizer as well as a portion of the feedback signal for the quantizer.
FIG. 1
is a block diagram of a generic prior art &Dgr;-&Sgr; A/D converter implementation at a system level. The analog input signal that is applied to input terminal
1
of the &Dgr;-&Sgr; A/D converter consists of both AC and DC components. A &Dgr;-&Sgr; quantizer
3
receiving the analog input signal may be of any order and may possess either a conventional linear or non-linear (as in high information delta modulation “HIDM” and adaptive delta modulation) transfer function, wherein the order is defined as the number of integrators embedded within the &Dgr;-&Sgr; A/D quantizer block
3
. The output of the &Dgr;-&Sgr; A/D quantizer is shown on line
5
as a 1-bit serial digital data stream having an output that is substantially “density” modulated and is proportional to the product of the input signal at
1
and the transfer function operated by the &Dgr;-&Sgr; A/D quantizer
3
.
The output
5
of the quantizer
3
in prior art &Dgr;-&Sgr; A/D converters has been processed in a number of ways, including decimation, averaging, and digital filtering to arrive at a usable signal. These methods have been used in various combinations and have been combined with weighting of the decimated samples and dithering to improve the resolution attainable (and hence the ultimately realizable accuracy and signal-to-noise ratio) and conversion speed. As illustrated in
FIG. 1
, the output
5
of the &Dgr;-&Sgr; A/D quantizer block
3
is accordingly input to a signal processing stage
7
that may include a decimation block
9
, a weighting block
11
, and one or both of a digital finite impulse response (FIR) filter
13
and infinite impulse response (IIR) filters
15
to reduce the raw &Dgr;-&Sgr; A/D quantizer's serial output data to produce a high resolution output on line
17
. Although there are many advantages to implementing the &Dgr;-&Sgr; A/D conversion process over more conventional A/D conversion processes, such as flash and successive approximation, many of the prior art methods of &Dgr;-&Sgr; A/D conversion unfortunately suffer from a much longer data latency than can be tolerated in many applications, most notably in control systems.
FIG. 2
illustrates waveforms typical of those produced by the prior art &Dgr;-&Sgr; A/D quantizer block
3
when a sinusoidal analog signal is applied to input terminal
1
and a high frequency clock is applied to a digital delay on input line
19
, as discussed in FIG.
3
. As the analog input signal represented as waveform
21
changes, the duty cycle of the pulse train from the &Dgr;-&Sgr; A/D quantizer block
3
, i.e., the duty cycle of the “Q” output from D-flip-flop shown at
22
in
FIG. 3
, which is represented in
FIG. 2
as waveform
23
, follows the input waveform
21
. As shown by the portion of the pulse train enclosed by bracket
25
, the &Dgr;-&Sgr; A/D quantizer's serial output data on line
5
has a low short-term duty cycle over the interval, whereby it matches the sinusoidal input waveform
21
, which is shown just below the bracketed portion
25
, while the short-term duty cycle is higher over the bracketed interval
27
, whereby it again matches the input waveform
21
.
As set forth in the heretofore published literature, the output data from prior art &Dgr;-&Sgr; A/D quantizer has been processed in several different ways. The attempt of all these known methods has been to reduce the raw &Dgr;-&Sgr; A/D quantizer's serial output data in a manner which can discern the finest incremental step size in the shortest period of time at point
17
in FIG.
1
. In telecommunications parlance, this equates to maximizing the frequency response and dynamic range of the conversion process while maintaining a given minimum signal-to-noise ratio.
The methods by which such output data has been manipulated to achieve these goals are summarized here. Averaging over time is the simplest method for reducing the output bit stream from a &Dgr;-&Sgr; A/D quantizer. Accordingly, the number of HIGH or “1” states (see
FIG. 2
, number
29
) of the &Dgr;-&Sgr; A/D output waveform
23
are “counted” during a fixed measurement interval or time period, such as interval
31
. A ratio of the total time spent in the “1” state to the fixed measurement interval
31
equates to the average duty cycle measured over that interval. The resolution of this method is limited to 1/d, where d is the number of clock cycles
33
contained within the fixed interval
31
.
Increasing the measurement period
31
and increasing the ratio of measurement time to clock period to improve resolution results in a correspondingly longer net conversion time, which worsens latency. Increasing the clock frequency (waveform
33
) to improve the resolution is limited by the performance of an integrator portion of the &Dgr;-&Sgr; A/D quantizer. Other secondary effects due to parasitic circuit elements also appear as the clock rate is increased.
A running average method for reducing the output bit stream from the &Dgr;-&Sgr; A/D quantizer adds many low resolution measurements together. This method concatenates together many contiguous lower resolution measurements to produce data that is similar to an average-over-time measurement, as described above, having an equal overall period.
The running average method can be combined with a small dither signal
35
, as illustrated in
FIG. 1
, that is input through a mixer
37
to the basic average-over-time data reduction scheme described above. This method improves the resolution, but the dither must be filtered out.
The running average method can also be combined with a digital filter, which has been widely used to reduce the output data
5
from the &Dgr;-&Sgr; A/D quantizer
3
. The digital filter following the running average reduces both the duty cycle or “density” and inter-bit phasing information contained in the &Dgr;-&Sgr; quantizer output
5
in order to achieve an output on line
17
having a given precision and minimal latency, as compared to the previously mentioned prior art methods. This method is commonly implemented as mul

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