Synchronized fault tolerant reset

Details Synchronized fault tolerant reset Synchronized fault tolerant reset

1994-11-21

1996-07-16

Beausoliel, Jr., Robert W.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307409, 371 471, 375356, 375357, 3649501, 3649503, G06F 1100

Patent

active

055376550

ABSTRACT:
A synchronizing circuit comprises a plurality of substantially identical modules for receiving respective asynchronous input signals and respective local clock signals with the local clock signals of the respective modules being substantially synchronized. Each module of the synchronizing circuit comprises a de-metastabilizer stage, a global synchronizing stage and a majority edge detector and voter network. The de-metastabilizer stage receives the input signal of the module and provides an output signal free of glitches and metastable conditions, synchronized to the local clock signal. The global synchronizing stage receives the output signals of the de-metastabilizer stage of each module and provides respective output signals synchronized to the local clock signal. The majority edge detector and voter network receives the output signals of the global synchronizing stage and outputs a voted output signal synchronized to the other modules' voted output signals and to the local clock signal.

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patent: 5404363 (1995-04-01), Krause et al.

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