Synchronized DRAM control apparatus using two different clock ra

Details Synchronized DRAM control apparatus using two different clock ra Synchronized DRAM control apparatus using two different clock ra

1992-02-20

1993-01-12

Shaw, Dale M.

Boots, shoes, and leggings

3642382, 3642383, 3642384, 36494204, 364DIG1, 364DIG2, 36494205, 395550, 395725, G06F 1300

Patent

active

051796678

ABSTRACT:
A control apparatus for a computer is described that includes an arbiter circuit for selecting a first controller for supplying the memory of the computer with a first plurality of addresses from a first bus at a first rate and for selecting the second controller for supplying the memory of the computer with a second plurality of addresses from a second bus at a second rate. The first and second controllers are selected such that the first and second controllers do not supply the memory with more than one memory address at a time. A method for controlling the use of a computer bus is also described. A plurality of requests to use the bus are received. A length of a first period for use of the bus and a length of a second period for use of the bus are preselected. Each of the plurality of requests are granted.

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