Synchronized, digital sequential circuit

Details Synchronized, digital sequential circuit Synchronized, digital sequential circuit

1993-03-01

1994-06-14

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307269, 328 72, 328 75, H04L 700

Patent

active

053213688

ABSTRACT:
A synchronized, digital sequential circuit includes state-controlled memory elements, each having a clock input, at least two outputs being complementary to one another and at least two inputs, which are connected to a logical OR linkage or wired OR connection. At least two state-controlled memory elements are connected in series. A first memory element performs the OR linkage or operation and a second memory element performs the AND linkage or operation of a combinatorial logic function. The settling time of a memory element and the delay time for forming the OR and AND linkages or operations coincide. Therefore, a high speed of operation is possible in the sequential circuit.

REFERENCES:
patent: 4607172 (1986-08-01), Frederiksen et al.
patent: 4748417 (1988-05-01), Spengler
patent: 4771441 (1988-09-01), Spengler et al.
patent: 4873456 (1989-10-01), Olisar et al.
German Publication "Halbleiter-Schaltungstechnik", Tietze et al. (1983) p. 234 6th Edition.
German Publication "Halbleiter-Schaltungstechnik", Tietze et al. (1985) pp. 259-261 7th Edition.
Electronic Circuits, Tietze et al, pp. 211, 212, 234-236 (1991).

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