Synchronized data capturing circuits using reduced voltage...

Details Synchronized data capturing circuits using reduced voltage... Synchronized data capturing circuits using reduced voltage...

1999-08-19

2003-12-23

Ghebretinsae, Temesghen (Department: 2631)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C327S141000

Reexamination Certificate

active

06668031

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to circuits for synchronizing data capture in an integrated circuit. More particularly, the present invention relates to circuits for synchronizing data capture that are capable of utilizing reduced voltage signals to reduce power consumption and/or to improve performance.
In any integrated circuit (IC), data signals often need to be transmitted from one circuit at one location on the IC to a receiving circuit at another location on the IC. As is well known by those skilled in the art, the data contained in the data signal is present in well defined data cycles, each of which has a finite period during which the data is valid for capture. Given that a data cycle is valid only for a limited period of time, it is crucial to ensure that the receiving circuit captures data during this relatively short period of time. This is particularly true in modern high speed IC's, which vastly reduce the duration of the data valid period, i.e., the time period during which data capturing must be performed.
To address the problem of properly capturing data at the receiving circuit during the limited time during which the data cycle is valid, timing or clock signals may be furnished to the receiving circuit. The use of a synchronized data capture circuit to synchronize data capture at the receiving circuit is well known. In general, if the timing signal tracks the data signal properly, the receiving circuit can depend on the timing information furnished in the timing signal to decide when to capture the data contained in the data signal.
To facilitate discussion,
FIG. 1A
illustrates a prior art circuit
100
for synchronizing data capture at a receiving circuit on the IC. Circuit
100
is shown in include a timing delay/driver
102
, a data delay/driver
104
, and a clocked data driver
106
. A data signal
108
is shown input into data delay/driver
104
, which is clocked by a control signal
110
, to produce a clocked data signal
112
. The same control signal
110
also clocks timing delay/driver
102
, producing a timing signal
114
. Timing delay/driver
102
and data delay/driver
104
ensure that timing signal
114
properly tracks clocked data signal
112
for the specific IC on which circuit
100
is implemented to allow clocked data driver
106
to properly capture the data contained in clocked data signal
112
based on the timing information furnished by timing signal
114
. The captured data is shown output from clocked data driver
106
as output data
116
in FIG.
1
A. The data synchronizing circuit of
FIG. 1A
is well known and will not be belabored further for the sake of brevity.
Although circuit
100
of
FIG. 1A
accomplishes the function of synchronizing data capture, there are significant disadvantages. One major disadvantage of the configuration shown in
FIG. 1A
relates to the fact prior art circuit
100
needs to operate with full swing signals (i.e., signals having the full rail-to-rail voltage swing of the IC) to perform synchronized data capture. More specifically, prior art circuit
100
is incapable of utilizing reduced voltage signals to perform the synchronized data capture task. As the term is employed herein, reduced voltage signals refer to signals whose amplitude is within a reduced voltage range, i.e., a voltage range that is lower than the full V
DD
, the power supply at which the peripheral circuits operate. In some cases, the reduced voltage level maybe low enough (e.g., 1V) that it approaches the threshold voltage of the transistors (typically at around 0.7V or so). Since reduced voltage signals are useful in reducing circuit power consumption and/or improving performance, the inability of prior art circuit
100
to employ reduced voltage signals to perform its synchronized data capture task represents a serious shortcoming.
One reason underlying the inability of prior art circuit
100
to employ reduced voltage signals to perform synchronized data capture relates to one of its basic building blocks, the CMOS inverter. CMOS inverters are a basic building block of delay circuits, such as those present in timing/delay driver
102
and data delay/driver
104
. To facilitate discussion,
FIG. 1B
depicts a simple CMOS inverter
150
, which includes a p-FET transistor
152
coupled in series with an n-FET transistor
154
between V
DD
and ground.
Consider first the situation wherein a full swing signal is employed at the input of CMOS inverter
150
. When input signal A at the input of CMOS inverter
150
is high at the V
DD
level, p-FET
152
is off and n-FET
154
is on, causing output signal B to be pulled to ground. Conversely, when input signal A at the input of CMOS inverter
150
is low at the ground level, p-FET
152
is on and n-FET
154
is off, causing output signal B to be pulled to V
DD
. In this case, CMOS inverter
150
functions correctly.
Now consider the situation wherein a reduced voltage signal is employed as an input signal A to CMOS inverter
150
. If the reduced voltage signal is, for example, 1 volt, a high input signal A not only causes n-FET
154
to be on as expected but also causes p-FET
152
to be softly on (i.e., not fully turning p-FET
152
off). In this case, the leakage current through p-PET
152
degrades the signal at the output of CMOS inverter
150
, which may cause other circuits to misinterpret the logic level represented by output signal B of CMOS inverter
150
. Furthermore, the leakage current through p-PET
152
to ground also causes CMOS inverter
150
to consume an unacceptable amount of power. Because of these issues and others, reduced voltage signals have not, to date, been employed in synchronized data capturing circuits to perform the synchronized data capture task.
As can be appreciated from the foregoing, there are desired synchronized data capturing circuits and methods therefore that can utilize reduced voltage signals to reduce power consumption and/or to increase performance.
SUMMARY OF THE INVENTION
The invention relates, in one embodiment, to a synchronized data capture circuit configured to synchronize capturing of data in a data signal with a timing signal in an integrated circuit. The synchronized data circuit employs voltage signals having a reduced voltage level, the data signal and the timing signal having a first voltage level higher than the reduced voltage level. The synchronized data capture circuit includes a timing driver circuit arranged to receive the timing signal. The timing driver circuit outputs a reduced voltage timing signal having the reduced voltage level. There is included a data driver circuit arranged to receive the data signal and the timing signal, the data driver outputting a reduced voltage clocked data signal having the reduced voltage level. There is further included a data clocking circuit coupled to the timing driver circuit and the data driver circuit. The data clocking circuit is arranged to receive the reduced voltage timing signal and the reduced voltage clocked data signal. The data clocking circuit outputs a synchronized capture data signal having the first voltage level higher than the reduced voltage level.
In another embodiment, the invention relates to a method for synchronizing capturing of data in a data signal with a timing signal in an integrated circuit. The method employs voltage signals having a reduced voltage level to accomplish the synchronized data capturing. The data signal and the timing signal have a first voltage level higher than the reduced voltage level. The method includes receiving the timing signal using a timing driver circuit and outputting, responsive to the timing signal, a reduced voltage timing signal having the reduced voltage level from the timing driver circuit. The method further includes receiving the data signal and the timing signal using a data driver circuit and outputting, responsive to the data signal and the timing signal, a reduced voltage clocked data signal having the reduced voltage level from the data driver circuit. There is further included pe

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