Television – Synchronization – Sync separation
Reexamination Certificate
1999-03-04
2001-08-07
Eisenzopf, Reinhard J. (Department: 2614)
Television
Synchronization
Sync separation
C348S530000, C348S521000
Reexamination Certificate
active
06271889
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention generally relates generally to synchronization pulse detection and more particularly to detection of synchronization pulses used in video signals.
As is known in the art, it is frequently required to provide a synchronization pulse prior to the active video information portion of a signal. For example, with video signal such as that shown in
FIG. 1
, each time a line, or segment, of video information
25
is provided, such line, or segment, is preceded with a horizontal synchronization pulse (i.e., Hsync). Thus, as shown in
FIGS. 1 and 1A
, each Hsync has a substantially non-time varying tip portion disposed between a pair of substantially time varying transition portions. The Hsync is preceded by a “front porch” and is terminated by a “back porch”. The “color burst” signal resides within the “back porch”. The “front porch” and “back porch” porch signals are at the “blanking level”. The active video information
25
is provided between the termination of the “back porch” and the “front porch” of the next Hsync.
Horizontal synchronization pulses (Hsyncs) in video signals are used to identify the begin of a line, or segment, of video information
25
. Hence, the accurate detection of the Hsync is crucial to the correct processing of the contents of a horizontal line, or segment, of video information
25
. This is true for analogue video as well as its digitized equivalent. In some Hsync detection systems, the 50% point of their falling edge is used as a reference point for the timing of the rest of the line, or segment, of video. In order to detect an Hsync, many detection circuits rely on the fact that the Hsync extends substantially below the “blanking level” for a considerable length of time. In some of these systems, Hsync detection has been carried out by comparing the actual video signal amplitude with a threshold amplitude set below the amplitude of the “blanking level”. Various filtering algorithms have been developed to avoid false triggering, for instance triggering on short glitches in the video signal. The threshold amplitude in the simplest implementation is of a DC nature. More advanced developments make the threshold amplitude adaptive to the incoming video signal.
The underlying assumption for all these algorithms is that the “blanking level” is known by the time Hsync detection takes place. This may not necessarily be the case since the transmission of a video signal usually trends to distort, or even lose, the DC value of a video signal. Many pieces of video equipment also rely on AC-coupling to connect video sources to them. As a result, the “blanking level” of the video signal is unknown. In practice, video signal clamp circuits are used to restore the DC value (See, for example U.S. Pat. No. 5,003,564). Only after the clamping process is finished, and the clamping control loop has settled, can one safely assume any DC value (e.g., “blank level”, Hsync tip value, etc.) of the video signal to have been restored and therefore be known. Thereafter, the threshold value for Hsync detection can be determined by offsetting from the “blanking level”.
While these techniques may be adequate for standard video signals from good quality signal sources under conditions where a fast lock-in time is not of high importance, they are very sensitive to DC shifts within the video signal. Furthermore, the initial lock-in depends on a successful clamp (i.e., successful restoration of the DC value). There also is a time penalty with this technique since the clamping and Hsync detection now become sequential tasks. Improved versions of Hsync detection use adaptive thresholds (See, for example, U.S. Pat. No. 5,576,770) which produce an adaptively restored DC value. While this provides a more robust function of the detection circuit during lock, it still relies on the performance of the clamping circuit (i.e., DC restoration) for initial lock and uses a principle known as “sync slicing”, i.e., the comparison of a signal amplitude with the adaptively restored pseudo DC value.
SUMMARY OF THE INVENTION
In accordance with the present invention, a synchronization pulse detection circuit is provided which determines time varying properties an input signal having the synchronization pulse and, from such determined time varying properties detects when such time varying properties have a shape of a synchronization pulse.
Such synchronization pulse detection is independent of any DC value of the signal. Detection of the synchronization pulse is based on detecting a shape in the signal rather than relying on a comparison of the signal with a DC value. To put it another way, the detection process scans the signal for a known shape (i.e., signature characteristic) of the signal rather than for a DC, or pseudo DC, value crossing.
In accordance with one embodiment of the invention, a synchronization pulse detector is provided for detecting a synchronization pulse within an input signal. The input signal has “level” portions (i.e., substantially non-time varying portions) and “transition” portions (i.e., substantially time varying portions). The pulse detector includes a pulse shape detector for determining each time the input signal has a proper sequence of a first “level” portion, followed by a first “transition” portion, followed by a second “level” portion, followed by a second “transition” portion followed by a third “level” portion, one of the first and second “transition” portions being positive and the other one of the first and second “transition” portions being negative. Each time such sequence is determined, a pulse_shape detected pulse is produced.
In accordance with another feature of the invention, an evaluator is provided to reject invalid pulse_shape detected pulses. The evaluator includes a time window for determining whether such shape_detected pulses are produced at a predetermined rate expected for a series of the synchronization pulses. The evaluator includes a voltage window responsive to the produced shape_detected pulses and their associated values of the second “level” portions for determining whether the average value of one of such produced second “level” portions is substantially lower or the same, but not higher than the lowest DC value detected within the time-equivalent of the last line, or segment, of video. The evaluator may include both the time window and the voltage window. The voltage window is mainly used to acquire an initial lock to an unknown and not yet clamped video signal.
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patent: 4722004 (1988-01-01), Miyamoto et al.
patent: 4792852 (1988-12-01), Narusawa
patent: 4829377 (1989-05-01), Becker et al.
patent: 5003564 (1991-03-01), Fling
patent: 5053869 (1991-10-01), Pletz-Kirsch
patent: 5432559 (1995-07-01), Bruins et al.
patent: 5539343 (1996-07-01), Yamashita et al.
Böhm Christian Willibald
Daly Michael Patrick
Heffernan Kieran
Analog Devices Inc.
Eisenzopf Reinhard J.
Samuels , Gauthier & Stevens, LLP
Tran Trang U.
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