Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Patent
1997-05-19
2000-12-05
Luu, Matthew
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
345504, G06T 120
Patent
active
061573957
ABSTRACT:
Synchronization of frame buffer swapping among computer graphics pipelines in a multi-pipeline display system: The pipelines are arranged in a closed daisy chain loop. One pipeline is configured as master; the others are configured as slaves. The master swaps its frame buffers and propagates a master swap signal through the daisy chain. As each slave recognizes the signal, it swaps its own buffers. Each slave propagates a feedback signal back to the master to indicate whether the slave is ready to swap its buffers again. The master waits until the feedback signal indicates that all slaves are ready to swap their buffers before the master will swap its own buffers a second time. The process repeats when the master swaps its buffers a second time.
A first synchronization control system is coupled to a first pipeline and has a first daisy chain input and a first daisy chain output. A second synchronization control system is coupled to a second pipeline and has a second daisy chain input and a second daisy chain output. The first synchronization control system asserts the first daisy chain output when the first pipeline swaps its buffers and unasserts the first daisy chain output when the first pipeline is ready to swap its buffers again. The first synchronization control system indicates, when the first daisy chain input is asserted, to the first pipeline that it should not swap its buffers. The second synchronization control system indicates, when the second daisy chain input transitions from unasserted to asserted, to the second pipeline that it should swap its buffers. The second synchronization control system asserts the second daisy chain output whenever either the second pipeline is not ready to swap its frame buffers, or the second daisy chain input is asserted.
REFERENCES:
patent: 4495594 (1985-01-01), Eggebrecht et al.
patent: 4523226 (1985-06-01), Lipton et al.
patent: 4710876 (1987-12-01), Cline et al.
patent: 4720708 (1988-01-01), Takeda et al.
patent: 4760388 (1988-07-01), Tatsumi et al.
patent: 5241389 (1993-08-01), Bilbrey
patent: 5289577 (1994-02-01), Gonzales et al.
patent: 5416510 (1995-05-01), Lipton et al.
patent: 5488952 (1996-02-01), Schoolman
patent: 5493595 (1996-02-01), Schoolman
patent: 5523886 (1996-06-01), Johnson-Williams et al.
patent: 5572250 (1996-11-01), Lipton et al.
patent: 5790113 (1998-08-01), Perlman et al.
patent: 5794016 (1998-08-01), Kelleher
patent: 5805149 (1998-08-01), Yuki et al.
patent: 5805913 (1998-09-01), Guttag et al.
patent: 5821989 (1998-10-01), Lazzaro et al.
patent: 5894312 (1999-04-01), Ishiwata et al.
Lenny Lipton, "Stereo-Vision Formats For Video And Computer Graphics", Printed from http://www.sgi.com/Products/hardware/graphics/technology/graphics.html in Apr. 1997.
Silicon Graphics Promotional Literature, "Infinite Reality Graphics For Stunning Real-Time Interactivity". Printed from: http://www.sgi.com/Products/hardware/graphics/technology/graphics.html in Apr. 1997.
IEEE Transactions on Consumer Electronics, vol. 34, No. 3, Aug. 1988, pp. 536-542 "3-Dimensional Personal Computer System".
Hart Kevin M.
Hewlett--Packard Company
Luu Matthew
LandOfFree
Synchronization of frame buffer swapping in multi-pipeline compu does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Synchronization of frame buffer swapping in multi-pipeline compu, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronization of frame buffer swapping in multi-pipeline compu will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-966015