Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Patent
1994-12-06
2000-02-29
Myers, Paul R.
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
Least weight routing
G06F 900
Patent
active
060321733
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to a computer system having several interconnected processors each associated with a memory, the memories all having a common storage area to which the processors have access.
In computer systems having several processors, which, for example, communicate with one another via a bus and jointly execute different tasks, it is necessary to synchronize the processing. This means that a change of a processor state of operation to another state of operation and/or the execution of system jobs or rather user jobs by the processors must be handled in a synchronous manner.
DE-OS 39 11 407 discloses a redundant computer system having several processors each associated with a memory. In each memory, a storage area is associated with each computer into which storage area the relevant computer enters data. Each computer reads out the data from its associated memory areas and supplies the data it reads out to a voter which performs a voter-based evaluation and reports any possible deviation in the supplied data as an error. During normal operation, the same data are present nine times and the lines to the memory units must be laid out three times.
SUMMARY OF THE INVENTION
The present invention is to simplify the known computer system in the interest of synchronization of changes in the state of operation of the processors and/or synchronous job processing.
In accordance with the present invention, to synchronize changes in the state of operation of the processors and/or to handle processor jobs in a synchronous manner, the first processor to reach a predetermined synchronization point during execution of a process enters a data set into the storage area and interrupt controllers associated with the processors detect a change in the data set, generate interrupt signals and feed them to the processors so that a change in the state of operation of the processors and/or synchronous job processing is initiated.
Time critical changes in the state of operation and/or synchronous job processing are carried out immediately after initiation. After initiation, all non-time-critical changes in the state of operation are then carried out simultaneously when all of the processors have reached corresponding synchronization points during their process execution.
BRIEF DESCRIPTION OF THE DRAWINGS
Based on the exemplary embodiments depicted in the drawings, the present invention will be explained along with its refinements and advantages.
FIG. 1 illustrates a block diagram of a computer system.
FIG. 2 illustrates states of operation and synchronization points of a processor.
FIG. 3 illustrates the structure of a common storage area.
DETAILED DESCRIPTION
In FIG. 1, processors of central processing units of a computer system are designated as P1, P2, P3 and a memory S1, S2, S3 is associated with each of these processors, respectively. These processors P1, P2, P3 are interconnected via a system bus SYB which is equipped with data, address and control lines that are known per se. The memories S1, S2, S3 all have a common storage area SB to which the processors P1, P2, P3 have read access via respective lines L1, L2, L3, whereas write accesses take place via the system bus SYB. Three programmable interrupt controllers belonging to the respective processors P1, P2, P3 are designated as IC1, IC2, IC3. These interrupt controllers detect a change in a data set stored in the storage area SB during a write access, generate interrupt signals and feed them to the associated processors P1, P2, P3 via lines U1, U2, U3. If a processor P2, P3 which reaches a synchronization point during its execution of a process writes a data set into the storage area SB, thereby changing the data set that was already stored, the interrupt controllers generate an interrupt signal. The processors change their current state of operation as a result and/or simultaneously start the execution of system jobs or user jobs.
To clarify the synchronization of the change in a state of operation, FIG. 2 shows states
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Myers Paul R.
Siemens Aktiengesellschaft
LandOfFree
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