Synchronization method and elastic buffer circuit

Details Synchronization method and elastic buffer circuit Synchronization method and elastic buffer circuit

1988-06-28

1989-04-18

Griffin, Robert L.

Pulse or digital communications

Spread spectrum

Direct sequence

375113, 370108, H04L 2536, H04L 2540

Patent

active

048233650

ABSTRACT:
An asynchronous communication system includes a clock recovery circuit (2) to which the received signal (1) is applied and which provides recovered data (3) to a frame delimiter detector (4). The frame delimiter detector in turn generates a frame start signal to a frame sync generator (16) and provides asynchronous data (5) to an elastic buffer (7) which provides as its output the synchronized data (8). The clock recovery circuit also provides a recovered clock signal (9) to a clock guarding circuit (12). The clock guarding circuit (12) receives a local clock signal (11) and produces a guarded clock signal (13) and a data clock signal (14), both of which are supplied to the frame sync generator and the elastic buffer. The frame sync generator produces a frame sync signal having a duration determined by the active edges of the guarded clock and data clock signals, and this signal is used to load a mask pattern in the elastic buffer. The synchronization method uses the guarded clock signal derived from the recovered clock signal so that the recovered clock signal cannot switch within certain zones on either side of each active edge of the data clock signal.

REFERENCES:
patent: 3825683 (1974-07-01), Pitroda et al.
patent: 4301417 (1981-11-01), Jansen et al.
patent: 4392234 (1983-07-01), Maruta
patent: 4429386 (1984-01-01), Graden
patent: 4525849 (1985-06-01), Wolf
patent: 4580279 (1986-04-01), Kahn
patent: 4764942 (1988-08-01), Shigaki et al.

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