Synchronization mechanism for a multiprocessing system

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G06F 900, G06F 100

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active

046637087

ABSTRACT:
A synchronization mechanism is disclosed for controlling devices or sub-systems connected to a common bus in a multiprocessing system so that the devices are kept in step one with the other when performing sequences of operations. More specifically, the mechanism ensures that no device can start its (i+1)th operation until all devices have completed their ith operation. This is achieved by providing each device with three synchronizing logic blocks (LB1, LB2, LB3) (LB', LB2', LB3') each of which functions to generate control signals (p, q, r respectively) on associated control lines at the end of selected operations in the sequence of operations. The control lines monitoring the performance of corresponding operations in all the devices are each applied via logic circuits (L1 or L2 or L3 as appropriate) (L1' or L2' or L3') to one of three selected bus lines (P, Q, R respectively). The logic circuits operate to produce a bus control signal on the selected bus line only when all of the corresponding operations have been completed by all the devices. As soon as a bus control signal is generated on one of the bus lines all devices start performing the next operation in the respective sequences.

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