Synchronization loss tolerant cyclic error checking method and a

Details Synchronization loss tolerant cyclic error checking method and a Synchronization loss tolerant cyclic error checking method and a

1980-09-08

1983-03-22

Atkinson, Charles E.

Excavating

371 2, 371 47, G06F 1110

Patent

active

043778631

ABSTRACT:
In a data processing system wherein a binary data message is protected by cyclic check codes, synchronization loss tolerance is incorporated by performing a binary transformation after encoding the message but prior to transmitting it or writing it to storage and by performing an inverse binary transformation upon receiving it or reading it from storage but prior to error checking. In one embodiment the transformation involves complementing a plurality of bits. In an alternate embodiment the transformation involves reversing the sequence of a plurality of contiguous bits.

REFERENCES:
patent: 3398400 (1968-08-01), Rupp et al.
patent: 3466601 (1969-09-01), Tong
patent: 3471830 (1969-10-01), McRae et al.
patent: 3560924 (1971-02-01), McBride
patent: 3753228 (1973-08-01), Nickolas et al.
patent: 4059825 (1977-11-01), Greene
patent: 4283786 (1981-08-01), Okamura
Ide and Sawtschenko, Data Synchronism Checking, IBM Technical _Disclosure Bulletin, vol. 7, No. 12, May 1965, pp. 1162-1163.
Bahl and Tang, Shortened Cyclic Code etc., IBM Technical Disclosure Bulletin, vol. 16, No. 6, Nov. 1973, pp. 2028-2030.

Affiliated with

Also associated with

Rating

Synchronization loss tolerant cyclic error checking method and a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Synchronization loss tolerant cyclic error checking method and a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronization loss tolerant cyclic error checking method and a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1872239