Pulse or digital communications – Synchronizers – Synchronization failure prevention
Reexamination Certificate
1998-03-11
2001-01-09
Pham, Chi H. (Department: 2731)
Pulse or digital communications
Synchronizers
Synchronization failure prevention
C375S354000
Reexamination Certificate
active
06173023
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to synchronization equipment, and more particularly to synchronization equipment which, after simple hardware installation and software setting, establishes a synchronization network with an existing network and SDH (Synchronous Digital Hierarchy) elements, etc. that do not support SSMB (Synchronization Status Message Half Byte).
2. Description of the Related Art
In recent years, SDH elements that use an SSMB signal to switch from one timing source to another for network synchronization have been increasing in number. The SSMB signal is transmitted using the low-order four bits of the S
1
byte (formerly Z
1
#1 byte) carried in the multiplex section overhead (MSOH) of an STM-n (Synchronous Transfer Mode-n) signal.
As shown in
FIG. 7
, described subsequently, the SSMB information itself is defined in the binary code table of ITU-T G.708, where four-bit signals, in various combinations of four bits, are each defined in relation to SDH synchronization quality. For example, “0010 (02h)” indicates the synchronization quality equivalent to G.811 (primary timing source using a cesium atomic oscillator), and “1111” is defined as “Don't use for sync.”
FIGS. 1A
to
1
C show an operational example of a network that supports SSMB.
In
FIG. 1A
, network element
1
(NE
1
) sets priority
1
for an external clock input (External Input) and priority
2
for an input line
2
(Line
2
). Further, network element
2
(NE
2
) sets priority
1
for an input line
1
(Line
1
) and priority
2
for an input line
4
(Line
4
). Similarly, network element
3
(NE
3
) sets priority
1
for an input line
3
(Line
3
) and priority
2
for an external clock input (External input). In the initial state, the network elements
1
,
2
, and
3
are each set to select the priority
1
side.
The network element
1
is connected to a primary synchronization clock generator (Primary Clock) constructed from a cesium atomic oscillator, and sends the SSMB value “02h”, representing the synchronization quality based on the primary clock, to its downstream network element
2
as the S
1
byte signal in the STM multiplex section overhead on Line
1
. Likewise, the network element
2
sends the SSMB value “02h” to the network element
3
as the S
1
byte signal in the STM multiplex section overhead on Line
3
. Here, the SSMB value of Lines
2
and
4
is set to “0Fh” to prevent a timing loop. In this way, the network elements
1
,
2
, and
3
are slave-synchronized to the primary synchronization clock signal from the primary synchronization clock generator.
Next, if a failure occurs in the primary synchronization clock generator or on its output line, as shown in
FIG. 1B
, the network element
1
is put in a holdover state and remains in that state. With this change in the synchronization quality, the network element
1
changes the SSMB value from “02h” to “0Bh” (SETS—Synchronization Equipment Timing Source), and sends the SSMB value to its downstream network element
2
via Line
1
. The network element
2
sends the same SSMB value “0Bh” to its downstream network element
3
via Line
3
. As a result, the entire network is synchronized to the holdover of the network element
1
.
In
FIG. 1C
, the network element
3
compares the synchronization quality (SSMB value “0Bh) on Line
3
of priority
1
with the synchronization quality (SSMB value “04h”) of the clock being applied at the external clock input (External Input) of priority
2
from a secondary synchronization clock generator (Secondary Clock) constructed from a rubidium atomic oscillator, selects the priority
2
side providing the better equality, and sends the SSMB value “04h” to the network element
2
via Line
4
. The network element
2
performs a similar comparison to select the better quality priority
2
side, and sends the SSMB value “04h” to the network element
1
via Line
2
.
Next, the network element
1
selects the priority
2
side providing the higher synchronization quality than its own holdover. As a result, the network elements
1
,
2
, and
3
are now slave-synchronized to the secondary synchronization clock signal from the secondary synchronization clock generator. Further, the SSMB value of Lines
1
and
2
is changed to “0Fh” to prevent a timing loop.
FIGS. 2A and 2B
show an example of an environment where a network and SDH elements that support SSMB coexist with an existing network and SDH elements that do not support SSMB.
As shown in
FIGS. 2A and 2B
, in the existing SSMB non-supporting network and SDH elements (indicated by oblique hatching), “1111” indicating a not-used state is often set in the S
1
byte. Accordingly, in the SSMB supporting network and SDH elements (indicated by dots) that are slaved to them, a decision is made that the timing source cannot be used (“Don't use for sync.”). As a result, there has been the problem that synchronization cannot be established successfully for the SSMB supporting network and SDH elements slaved to the SSMB non-supporting network and SDH elements.
SUMMARY OF THE INVENTION
In view of the above-described problem, it is an object of the present invention to provide synchronization equipment which, after simple hardware installation and software setting, can establish synchronization between an SSMB supporting network and SDH elements and an existing SSMB non-supporting network and SDH elements in an environment where such networks and elements are mixed.
According to the present invention, there is provided synchronization equipment comprising: a timing source interface section for interfacing with multiple kinds of timing sources; a timing source switching section for outputting one timing source by switching its input between a plurality of timing sources which have been selected in the timing source interface section and assigned prescribed priority; a PLL section for generating an equipment clock by synchronizing to the timing source selected and output from the timing source switching section; a failure detection section for detecting a failure of each of the plurality of timing sources assigned the prescribed priority; a failure monitoring section for monitoring failure detection information from the failure detection section, and for outputting in the event of detection of a timing source failure a timing source switching control signal directing switching to a timing source having the highest priority among the timing sources other than the failure-detected timing source; an SSMB interface section for interfacing with an SSMB bus; an SSMB-to-quality conversion section for converting SSMB information supplied from the SSMB interface section into corresponding synchronization quality information; a timing source selection section for outputting a timing source switching control signal based on the synchronization quality information supplied from the SSMB-to-quality conversion section; and a selection section for selecting either the timing source switching control signal from the failure monitoring section or the timing source switching control signal from the timing source selection section in accordance with an instruction from prescribed selection instruction means. The prescribed selection instruction means is an equipment controller that controls equipment operation, or is constructed from a manually operated switch mechanism.
According to the present invention, there is also provided synchronization equipment comprising: a synchronizer for performing synchronization control; and an STM-n channel unit, connected to a transmission line, for communicating SSMB information with the synchronizer, and wherein: an SSMB value to be sent to the STM-n channel unit from the synchronizer is set by an equipment controller controlling equipment operation, thereby enabling the STM-n channel unit to send an arbitrary SSMB value out onto the transmission line.
According to the present invention, there is also provided synchronization equipment, wherein, instead of setting the SSMB
Kidoku Naoto
Magome Toshikazu
Suzuki Hiroyuki
Tanonaka Koji
Fujitsu Limited
Helfgott & Karas P.C.
Pham Chi H.
Tran Khai
LandOfFree
Synchronization equipment does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Synchronization equipment, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Synchronization equipment will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2549616