Synchronization device for output stages, particularly for elect

Static information storage and retrieval – Addressing – Sync/clocking

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3652335, 365191, G11C 800

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active

056338341

ABSTRACT:
A device that synchronizes an output stage of an electronic memory by enabling the output stage of the memory device after data has been retrieved from the memory, the memory chip is enabled, and output of the memory data is requested. The device also can enable the output stage of the memory regardless of whether the data has been retrieved from the memory based upon receipt of a forced activation signal, and can enable the output stage of the memory for selected bits.

REFERENCES:
patent: 4858197 (1989-08-01), Aono et al.
European Search Report from European Patent Application 94830538.8, filed Nov. 18, 1994.
Patent Abstracts of Japan, vol. 10, No. 284 (P-501), Sep. 26, 1986 & JP-A-61 104397 Hitachi.

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