Synchronization detection circuit

Television – Synchronization – Sync separation

Patent

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Details

348521, 348500, H04N 508

Patent

active

057964440

ABSTRACT:
A synchronization detection circuit quickly detects resynchronization to a new input signal quickly when the input signal changes, etc. A frame synchronization detection circuit 3 synchronizes the frame pattern contained in, for example, the MUSE signal, etc., and a frame synchronizing signal (signal (IFP1)) formed in the MUSE decoder, pattern detection circuits 30, an integrating circuit 32, and a slicing circuit 36 function in concert to detect and output the frame pattern to a phase comparator 36 as a signal (SS). Phase comparator 36 and judging circuit 38 function in concert to detect nonsynchronization when the fact that the phase difference between signal (IFP1) formed by frequency dividing circuit 42 and signal (SS) exceeds the prescribed value is detected continuously for 8 frames or when the fact that the phase difference between signal (SS) and signal (IFP1) exceeds the prescribed value and the phase difference between signal (SS) and signal (IFP2) does not exceed the prescribed value is detected continuously for 2 frames, and gate circuit 40 initializes frequency dividing circuit 42 when nonsynchronization is detected and matches the phase of signal (IFP1) to the phase of signal (SS).

REFERENCES:
patent: 5148276 (1992-09-01), Furumiya et al.
patent: 5220411 (1993-06-01), Kitaura et al.

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