Synchronization correction circuit

Details Synchronization correction circuit Synchronization correction circuit

2006-01-03

2006-01-03

Phunkulh, Bob (Department: 2661)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S520000

Reexamination Certificate

active

06982994

ABSTRACT:
The synchronization signal generating section generates a packet synchronization signal PSYNC such that it is synchronized with the cycle of packets received from the master device. The interface control section generates a transfer clock PCMCLK used in transferring the data in the packets, from the internal clock. The interface control section measures the cycle of the packet synchronization signal PSYNC, and if the actual cycle of PSYNC is longer than the designated value, it makes the cycle of the transfer clock corresponding to the last data element in the packet longer than the cycle of the transfer clock corresponding to the other data elements, whereas if the actual cycle of PSYNC is shorter than the designated value, it makes the cycle of the transfer clock corresponding to the last data element in the packet shorter than the cycle of the transfer clock corresponding to the other data elements.

REFERENCES:
patent: 5570370 (1996-10-01), Lin
patent: 5757869 (1998-05-01), Sands et al.
patent: 5953378 (1999-09-01), Hotani et al.
patent: 5963605 (1999-10-01), Yasui
patent: 6278718 (2001-08-01), Eschholz
Naoki Sugiyama, “Core Technologies of Bluetooth System”, SPA vol. 67(3), pp. 53-56, Oct. 2000.

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