Synchronization compensating circuit for use in scanning type di

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307262, 328 63, 328 72, 328137, 328154, H03K 500, H03K 513

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active

051011182

ABSTRACT:
A synchronization compensating circuit for use in a scanning type display circuit, comprises a first multistage delay circuit receiving a basic clock for generating K delayed clocks, a second multistage delay circuit receiving an output of the first multistage delay circuit for generating L delayed clocks, and a timing signal generating circuit receiving a horizontal synchronization signal for generating a latch signal. A first selection signal generation circuit latches a first phase of the basic clock and the K delayed clocks in response to the latch signal, and a second selection signal generation circuit latches a second phase of the basic clock and the K delayed clocks in response to the latch signal. A third selection signal generation circuit latches the L delayed clocks in response to the latch signal. Each of the first to third selection signal generation circuit generates a selection signal corresponding to a received clock fulfilling a predetermined condition. A selection circuit receives the basic clock and the K and L delayed clocks for outputting a delayed clock corresponding to the selection signal outputted from the first signal generation circuit in preference to the selection signal from the second and third selection signal generation circuits, and a delayed clock corresponding to the selection signal outputted from the second selection signal generation circuit in preference to the selection signal from the third selection signal generation circuit when the selection signal is not outputted from the first selection signal generation circuit.

REFERENCES:
patent: 4290022 (1981-09-01), Puckette
patent: 4328588 (1982-05-01), Smithson
patent: 4999526 (1991-04-01), Dudley

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