Multiplex communications – Wide area network – Packet switching
Patent
1992-12-03
1994-01-25
Olms, Douglas W.
Multiplex communications
Wide area network
Packet switching
3701054, 375114, 375116, H04J 306
Patent
active
052822060
ABSTRACT:
A synchronous circuit includes a first circuit block operating in synchronism with a first clock signal, and a second circuit block operating in synchronism with a second clock signal having a frequency lower than that of the first clock signal. The first circuit block includes a frame synchronizing circuit for detecting a synchronous pattern contained in input data having a frame format having a supervisory control data part and an information part, the supervisory control data part including pointer information indicative of a beginning of the information part. The first circuit block includes a synchronizing unit for generating, from the synchronous pattern, a synchronizing control signal for synchronizing the operation of the second circuit block with the operation of the first circuit block. The first circuit block includes a pulse generator for generating a first frame pulse signal from the first clock signal. The second circuit block includes an information part detecting unit for generating a second frame pulse signal having a frequency lower than that of the first frame pulse signal from the second clock signal and the synchronizing control signal, the first frame pulse signal being synchronized with the beginning of the information part.
REFERENCES:
patent: 4453260 (1984-06-01), Inagawa et al.
patent: 4748623 (1988-05-01), Fujimoto
patent: 4984238 (1991-01-01), Watanabe et al.
patent: 5210754 (1993-05-01), Takahashi et al.
CCITT Recommendations G.707, G.708 and G.709 (Melbourne, 1988).
Ishihara Tomohiro
Kondo Ryuichi
Sudo Toshiyuki
Wakisaka Takaaki
Yamashita Haruo
Fujitsu Limited
Hsu Alpus H.
Olms Douglas W.
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